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Diffstat (limited to 'src/southbridge/intel/i82801cx')
-rw-r--r--src/southbridge/intel/i82801cx/i82801cx_ide.c4
-rw-r--r--src/southbridge/intel/i82801cx/i82801cx_lpc.c8
-rw-r--r--src/southbridge/intel/i82801cx/i82801cx_usb.c4
3 files changed, 8 insertions, 8 deletions
diff --git a/src/southbridge/intel/i82801cx/i82801cx_ide.c b/src/southbridge/intel/i82801cx/i82801cx_ide.c
index 2506b2f329..74c442c52c 100644
--- a/src/southbridge/intel/i82801cx/i82801cx_ide.c
+++ b/src/southbridge/intel/i82801cx/i82801cx_ide.c
@@ -18,7 +18,7 @@ static void ide_init(struct device *dev)
if (enable_primary) {
/* Enable first ide interface */
ideTimingConfig |= IDE_DECODE_ENABLE;
- printk_debug("IDE0 ");
+ printk(BIOS_DEBUG, "IDE0 ");
}
pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig);
@@ -27,7 +27,7 @@ static void ide_init(struct device *dev)
if (enable_secondary) {
/* Enable secondary ide interface */
ideTimingConfig |= IDE_DECODE_ENABLE;
- printk_debug("IDE1 ");
+ printk(BIOS_DEBUG, "IDE1 ");
}
pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig);
}
diff --git a/src/southbridge/intel/i82801cx/i82801cx_lpc.c b/src/southbridge/intel/i82801cx/i82801cx_lpc.c
index 4785242a79..9ac3e8326b 100644
--- a/src/southbridge/intel/i82801cx/i82801cx_lpc.c
+++ b/src/southbridge/intel/i82801cx/i82801cx_lpc.c
@@ -35,7 +35,7 @@ void i82801cx_enable_ioapic( struct device *dev)
dword |= (1 << 1); /* delay transaction enable */
dword |= (1 << 2); /* DMA collection buf enable */
pci_write_config32(dev, GEN_CNTL, dword);
- printk_debug("ioapic southbridge enabled %x\n",dword);
+ printk(BIOS_DEBUG, "ioapic southbridge enabled %x\n",dword);
// Must program the APIC's ID before using it
@@ -45,7 +45,7 @@ void i82801cx_enable_ioapic( struct device *dev)
// Hang if the ID didn't take (chip not present?)
*ioapic_index = 0;
dword = *ioapic_data;
- printk_debug("Southbridge apic id = %x\n", (dword>>24) & 0xF);
+ printk(BIOS_DEBUG, "Southbridge apic id = %x\n", (dword>>24) & 0xF);
if(dword != (2<<24))
die("");
@@ -105,7 +105,7 @@ void i82801cx_rtc_init(struct device *dev)
pmcon3 |= SLEEP_AFTER_POWER_FAIL;
}
pci_write_config8(dev, GEN_PMCON_3, pmcon3);
- printk_info("set power %s after power fail\n",
+ printk(BIOS_INFO, "set power %s after power fail\n",
pwr_on ? "on" : "off");
// See if the Safe Mode jumper is set
@@ -177,7 +177,7 @@ static void lpc_init(struct device *dev)
else
byte |= 1; // Return to S5
pci_write_config8(dev, GEN_PMCON_3, byte);
- printk_info("set power %s after power fail\n", pwr_on?"on":"off");
+ printk(BIOS_INFO, "set power %s after power fail\n", pwr_on?"on":"off");
/* Set up NMI on errors */
byte = inb(0x61);
diff --git a/src/southbridge/intel/i82801cx/i82801cx_usb.c b/src/southbridge/intel/i82801cx/i82801cx_usb.c
index 258581a78b..00b668d023 100644
--- a/src/southbridge/intel/i82801cx/i82801cx_usb.c
+++ b/src/southbridge/intel/i82801cx/i82801cx_usb.c
@@ -10,14 +10,14 @@ static void usb_init(struct device *dev)
#if 0
uint32_t cmd;
- printk_debug("USB: Setting up controller.. ");
+ printk(BIOS_DEBUG, "USB: Setting up controller.. ");
cmd = pci_read_config32(dev, PCI_COMMAND);
pci_write_config32(dev, PCI_COMMAND,
cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
- printk_debug("done.\n");
+ printk(BIOS_DEBUG, "done.\n");
#endif
}