diff options
Diffstat (limited to 'src/southbridge/intel/i82801dx/i82801dx_lpc.c')
| -rw-r--r-- | src/southbridge/intel/i82801dx/i82801dx_lpc.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/southbridge/intel/i82801dx/i82801dx_lpc.c b/src/southbridge/intel/i82801dx/i82801dx_lpc.c index a3130e164e..ae522c310b 100644 --- a/src/southbridge/intel/i82801dx/i82801dx_lpc.c +++ b/src/southbridge/intel/i82801dx/i82801dx_lpc.c @@ -53,14 +53,14 @@ static void i82801dx_enable_ioapic(struct device *dev) reg32 |= (1 << 1); /* Delayed transaction enable */ reg32 |= (1 << 2); /* DMA collection buffer enable */ pci_write_config32(dev, GEN_CNTL, reg32); - printk_debug("IOAPIC Southbridge enabled %x\n", reg32); + printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); *ioapic_index = 0; *ioapic_data = (1 << 25); *ioapic_index = 0; reg32 = *ioapic_data; - printk_debug("Southbridge APIC ID = %x\n", reg32); + printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32); if (reg32 != (1 << 25)) die("APIC Error\n"); @@ -107,7 +107,7 @@ static void i82801dx_power_options(device_t dev) * 1 == S5 Soft Off */ pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1); - printk_info("Set power %s if power fails\n", pwr_on ? "on" : "off"); + printk(BIOS_INFO, "Set power %s if power fails\n", pwr_on ? "on" : "off"); /* Set up NMI on errors. */ byte = inb(0x61); @@ -198,7 +198,7 @@ static void enable_hpet(struct device *dev) reg32 |= (code << 15); pci_write_config32(dev, GEN_CNTL, reg32); - printk_debug("Enabling HPET @0x%x\n", HPET_ADDR | (code << 12)); + printk(BIOS_DEBUG, "Enabling HPET @0x%x\n", HPET_ADDR | (code << 12)); } static void lpc_init(struct device *dev) |