diff options
Diffstat (limited to 'src/southbridge/intel/i82801ex')
| -rw-r--r-- | src/southbridge/intel/i82801ex/chip.h | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ex/i82801ex.c | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ex/i82801ex_ac97.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ex/i82801ex_early_smbus.c | 28 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ex/i82801ex_ehci.c | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ex/i82801ex_ide.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ex/i82801ex_lpc.c | 14 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ex/i82801ex_pci.c | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ex/i82801ex_sata.c | 6 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ex/i82801ex_smbus.h | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ex/i82801ex_uhci.c | 2 |
11 files changed, 35 insertions, 35 deletions
diff --git a/src/southbridge/intel/i82801ex/chip.h b/src/southbridge/intel/i82801ex/chip.h index 34a0a97ffd..f04fc3fd29 100644 --- a/src/southbridge/intel/i82801ex/chip.h +++ b/src/southbridge/intel/i82801ex/chip.h @@ -1,7 +1,7 @@ #ifndef I82801EX_CHIP_H #define I82801EX_CHIP_H -struct southbridge_intel_i82801ex_config +struct southbridge_intel_i82801ex_config { #define ICH5R_GPIO_USE_MASK 0x03 diff --git a/src/southbridge/intel/i82801ex/i82801ex.c b/src/southbridge/intel/i82801ex/i82801ex.c index bc5f04bf44..fc4164523a 100644 --- a/src/southbridge/intel/i82801ex/i82801ex.c +++ b/src/southbridge/intel/i82801ex/i82801ex.c @@ -25,7 +25,7 @@ void i82801ex_enable(device_t dev) (lpc_dev->device != PCI_DEVICE_ID_INTEL_82801ER_LPC)) { uint32_t id; id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); - if (id != (PCI_VENDOR_ID_INTEL | + if (id != (PCI_VENDOR_ID_INTEL | (PCI_DEVICE_ID_INTEL_82801ER_LPC << 16))) { return; } @@ -39,7 +39,7 @@ void i82801ex_enable(device_t dev) if (reg != reg_old) { pci_write_config16(lpc_dev, 0xf2, reg); } - + } struct chip_operations southbridge_intel_i82801ex_ops = { diff --git a/src/southbridge/intel/i82801ex/i82801ex_ac97.c b/src/southbridge/intel/i82801ex/i82801ex_ac97.c index 65502dd8cc..08efe1534d 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_ac97.c +++ b/src/southbridge/intel/i82801ex/i82801ex_ac97.c @@ -8,7 +8,7 @@ static void ac97_set_subsystem(device_t dev, unsigned vendor, unsigned device) { /* Write the subsystem vendor and device id */ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); } diff --git a/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c b/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c index 27bd3f2324..b07c77a94f 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c +++ b/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c @@ -35,7 +35,7 @@ static void smbus_write_byte(unsigned device, unsigned address, unsigned char va if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) { return; } - + print_debug("Unimplemented smbus_write_byte() called.\n"); #if 0 @@ -60,11 +60,11 @@ static void smbus_write_byte(unsigned device, unsigned address, unsigned char va /* poll for transaction completion */ smbus_wait_until_done(SMBUS_IO_BASE); -#endif +#endif return; } -static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, +static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, unsigned data1, unsigned data2) { unsigned char byte; @@ -73,11 +73,11 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, /* chear the PM timeout flags, SECOND_TO_STS */ outw(inw(0x0400 + 0x66), 0x0400 + 0x66); - + if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) { return -2; } - + /* setup transaction */ /* Obtain ownership */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); @@ -88,39 +88,39 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT); /* disable interrupts */ outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); - + /* set the device I'm talking too */ outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD); - + /* set the command address */ outb(cmd & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); - + /* set the block length */ outb(length & 0xFF, SMBUS_IO_BASE + SMBHSTDAT0); - + /* try sending out the first byte of data here */ byte=(data1>>(0))&0x0ff; outb(byte,SMBUS_IO_BASE + SMBBLKDAT); /* issue a block write command */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40, + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40, SMBUS_IO_BASE + SMBHSTCTL); for(i=0;i<length;i++) { - + /* poll for transaction completion */ if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) { return -3; } - + /* load the next byte */ if(i>3) byte=(data2>>(i%4))&0x0ff; else byte=(data1>>(i))&0x0ff; outb(byte,SMBUS_IO_BASE + SMBBLKDAT); - + /* clear the done bit */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); } diff --git a/src/southbridge/intel/i82801ex/i82801ex_ehci.c b/src/southbridge/intel/i82801ex/i82801ex_ehci.c index 17da5d94c6..8ae921d194 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_ehci.c +++ b/src/southbridge/intel/i82801ex/i82801ex_ehci.c @@ -11,7 +11,7 @@ static void ehci_init(struct device *dev) printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); cmd = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, + pci_write_config32(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER); printk(BIOS_DEBUG, "done.\n"); @@ -24,7 +24,7 @@ static void ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device) /* Enable writes to protected registers */ pci_write_config8(dev, 0x80, access_cntl | 1); /* Write the subsystem vendor and device id */ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); /* Restore protection */ pci_write_config8(dev, 0x80, access_cntl); diff --git a/src/southbridge/intel/i82801ex/i82801ex_ide.c b/src/southbridge/intel/i82801ex/i82801ex_ide.c index cd622907ab..bbab6f1cc0 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_ide.c +++ b/src/southbridge/intel/i82801ex/i82801ex_ide.c @@ -19,7 +19,7 @@ static void ide_init(struct device *dev) static void i82801ex_ide_set_subsystem(device_t dev, unsigned vendor, unsigned device) { /* This value is also visible in uchi[0-2] and smbus functions */ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); } diff --git a/src/southbridge/intel/i82801ex/i82801ex_lpc.c b/src/southbridge/intel/i82801ex/i82801ex_lpc.c index b97af3860a..8753db17e3 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_lpc.c +++ b/src/southbridge/intel/i82801ex/i82801ex_lpc.c @@ -89,7 +89,7 @@ static void set_i82801ex_gpio_direction( switch(config->gpio[i] & ICH5R_GPIO_SEL_MASK) { case ICH5R_GPIO_SEL_OUTPUT: val = 0; break; case ICH5R_GPIO_SEL_INPUT: val = 1; break; - default: + default: continue; } /* The caller is responsible for not playing with unimplemented bits */ @@ -121,7 +121,7 @@ static void set_i82801ex_gpio_level( case ICH5R_GPIO_LVL_LOW: val = 0; blink = 0; break; case ICH5R_GPIO_LVL_HIGH: val = 1; blink = 0; break; case ICH5R_GPIO_LVL_BLINK: val = 1; blink = 1; break; - default: + default: continue; } /* The caller is responsible for not playing with unimplemented bits */ @@ -152,7 +152,7 @@ static void set_i82801ex_gpio_inv( switch(config->gpio[i] & ICH5R_GPIO_INV_MASK) { case ICH5R_GPIO_INV_OFF: val = 0; break; case ICH5R_GPIO_INV_ON: val = 1; break; - default: + default: continue; } gpio_inv &= ~( 1 << i); @@ -195,7 +195,7 @@ static void i82801ex_gpio_init(device_t dev) /* Find the GPIO bar */ res = find_resource(dev, GPIO_BAR); if (!res) { - return; + return; } /* Set the use selects */ @@ -271,7 +271,7 @@ static void lpc_init(struct device *dev) /* Set up the PIRQ */ i82801ex_pirq_init(dev); - + /* Set the state of the gpio lines */ i82801ex_gpio_init(dev); @@ -283,7 +283,7 @@ static void lpc_init(struct device *dev) /* Disable IDE (needed when sata is enabled) */ pci_write_config8(dev, 0xf2, 0x60); - + enable_hpet(dev); } @@ -330,7 +330,7 @@ static void i82801ex_lpc_enable_resources(device_t dev) acpi_cntl = pci_read_config8(dev, 0x44); acpi_cntl |= (1 << 4); pci_write_config8(dev, 0x44, acpi_cntl); - + /* Enable the GPIO bar */ gpio_cntl = pci_read_config8(dev, 0x5c); gpio_cntl |= (1 << 4); diff --git a/src/southbridge/intel/i82801ex/i82801ex_pci.c b/src/southbridge/intel/i82801ex/i82801ex_pci.c index 2394844ba4..80c6e49bc0 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_pci.c +++ b/src/southbridge/intel/i82801ex/i82801ex_pci.c @@ -21,8 +21,8 @@ static void pci_init(struct device *dev) dword |= (1<<8); /* SERR# Enable */ dword |= (1<<6); /* Parity Error Response */ pci_write_config32(dev, 0x04, dword); -#endif - +#endif + word = pci_read_config16(dev, 0x1e); word |= 0xf800; /* Clear possible errors */ pci_write_config16(dev, 0x1e, word); diff --git a/src/southbridge/intel/i82801ex/i82801ex_sata.c b/src/southbridge/intel/i82801ex/i82801ex_sata.c index a490f2a8c3..9b340e9afd 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_sata.c +++ b/src/southbridge/intel/i82801ex/i82801ex_sata.c @@ -11,7 +11,7 @@ static void sata_init(struct device *dev) /* SATA configuration */ pci_write_config8(dev, 0x04, 0x07); pci_write_config8(dev, 0x09, 0x8f); - + /* Set timmings */ pci_write_config16(dev, 0x40, 0x0a307); pci_write_config16(dev, 0x42, 0x0a307); @@ -25,10 +25,10 @@ static void sata_init(struct device *dev) /* Combine ide - sata configuration */ pci_write_config8(dev, 0x90, 0x0); - + /* port 0 & 1 enable */ pci_write_config8(dev, 0x92, 0x33); - + /* initialize SATA */ pci_write_config16(dev, 0xa0, 0x0018); pci_write_config32(dev, 0xa4, 0x00000264); diff --git a/src/southbridge/intel/i82801ex/i82801ex_smbus.h b/src/southbridge/intel/i82801ex/i82801ex_smbus.h index 27acca494f..f330c0a5de 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_smbus.h +++ b/src/southbridge/intel/i82801ex/i82801ex_smbus.h @@ -10,7 +10,7 @@ #define SMBTRNSADD 0x9 #define SMBSLVDATA 0xa #define SMLINK_PIN_CTL 0xe -#define SMBUS_PIN_CTL 0xf +#define SMBUS_PIN_CTL 0xf #define SMBUS_TIMEOUT (100*1000*10) diff --git a/src/southbridge/intel/i82801ex/i82801ex_uhci.c b/src/southbridge/intel/i82801ex/i82801ex_uhci.c index fe80079d09..56536b7273 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_uhci.c +++ b/src/southbridge/intel/i82801ex/i82801ex_uhci.c @@ -12,7 +12,7 @@ static void uhci_init(struct device *dev) #if 1 printk(BIOS_DEBUG, "UHCI: Setting up controller.. "); cmd = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, + pci_write_config32(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER); |