1 files changed, 100 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801gx/usb.c b/src/southbridge/intel/i82801gx/usb.c
new file mode 100644
index 0000000000..00fddf7c65
--- /dev/null
+++ b/src/southbridge/intel/i82801gx/usb.c
@@ -0,0 +1,100 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "i82801gx.h"
+
+static void usb_init(struct device *dev)
+{
+	u32 reg32;
+	u8 reg8;
+
+	/* USB Specification says the device must be Bus Master */
+	printk(BIOS_DEBUG, "UHCI: Setting up controller.. ");
+
+	reg32 = pci_read_config32(dev, PCI_COMMAND);
+	pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
+
+	// Erratum
+	pci_write_config8(dev, 0xca, 0x00);
+
+	// Yes. Another Erratum
+	reg8 = pci_read_config8(dev, 0xca);
+	reg8 |= (1 << 0);
+	pci_write_config8(dev, 0xca, reg8);
+
+	printk(BIOS_DEBUG, "done.\n");
+}
+
+static void usb_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static struct pci_operations usb_pci_ops = {
+	.set_subsystem    = usb_set_subsystem,
+};
+
+static struct device_operations usb_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= usb_init,
+	.scan_bus		= 0,
+	.enable			= i82801gx_enable,
+	.ops_pci		= &usb_pci_ops,
+};
+
+/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
+static const struct pci_driver i82801gb_usb1 __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x27c8,
+};
+
+/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
+static const struct pci_driver i82801gb_usb2 __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x27c9,
+};
+
+/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
+static const struct pci_driver i82801gb_usb3 __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x27ca,
+};
+
+/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
+static const struct pci_driver i82801gb_usb4 __pci_driver = {
+	.ops	= &usb_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x27cb,
+};