summaryrefslogtreecommitdiff
path: root/src/southbridge/intel/i82801gx
diff options
context:
space:
mode:
Diffstat (limited to 'src/southbridge/intel/i82801gx')
-rw-r--r--src/southbridge/intel/i82801gx/smihandler.c7
1 files changed, 0 insertions, 7 deletions
diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c
index c6425dba51..2c21ea7757 100644
--- a/src/southbridge/intel/i82801gx/smihandler.c
+++ b/src/southbridge/intel/i82801gx/smihandler.c
@@ -212,7 +212,6 @@ static u32 reset_tco_status(void)
return reg32;
}
-
static void dump_tco_status(u32 tco_sts)
{
printk(BIOS_DEBUG, "TCO_STS: ");
@@ -232,12 +231,6 @@ static void dump_tco_status(u32 tco_sts)
printk(BIOS_DEBUG, "\n");
}
-/* We are using PCIe accesses for now
- * 1. the chipset can do it
- * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind
- */
-#include <arch/pci_mmio_cfg.h>
-
int southbridge_io_trap_handler(int smif)
{
switch (smif) {