diff options
Diffstat (limited to 'src/southbridge/intel/i82801gx')
| -rw-r--r-- | src/southbridge/intel/i82801gx/Kconfig | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx.h | 18 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx_azalia.c | 16 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx_lpc.c | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx_pci.c | 19 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx_pcie.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx_power.h | 27 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx_reset.c | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx_smi.c | 5 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx_smihandler.c | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx_watchdog.c | 1 |
12 files changed, 45 insertions, 51 deletions
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 9bc0815087..a784a880e4 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -20,4 +20,5 @@ config SOUTHBRIDGE_INTEL_I82801GX bool select IOAPIC + select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 1f320c5182..3ae440d568 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -47,6 +47,24 @@ extern void i82801gx_enable(device_t dev); #endif +#define MAINBOARD_POWER_OFF 0 +#define MAINBOARD_POWER_ON 1 +#define MAINBOARD_POWER_KEEP 2 + +#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL +#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON +#endif + +/* PCI Configuration Space (D30:F0): PCI2PCI */ +#define PSTS 0x06 +#define SMLT 0x1b +#define SECSTS 0x1e +#define INTR 0x3c +#define BCTRL 0x3e +#define SBR (1 << 6) +#define SEE (1 << 1) +#define PERE (1 << 0) + /* PCI Configuration Space (D31:F0): LPC */ #define SERIRQ_CNTL 0x64 diff --git a/src/southbridge/intel/i82801gx/i82801gx_azalia.c b/src/southbridge/intel/i82801gx/i82801gx_azalia.c index 2b9b24579b..60b7334c2c 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_azalia.c +++ b/src/southbridge/intel/i82801gx/i82801gx_azalia.c @@ -33,7 +33,7 @@ typedef struct southbridge_intel_i82801gx_config config_t; -static int set_bits(u8 * port, u32 mask, u32 val) +static int set_bits(u32 port, u32 mask, u32 val) { u32 reg32; int count; @@ -62,7 +62,7 @@ static int set_bits(u8 * port, u32 mask, u32 val) return 0; } -static int codec_detect(u8 * base) +static int codec_detect(u32 base) { u32 reg32; @@ -116,7 +116,7 @@ static u32 find_verb(struct device *dev, u32 viddid, u32 ** verb) * no response would imply that the codec is non-operative */ -static int wait_for_ready(u8 *base) +static int wait_for_ready(u32 base) { /* Use a 50 usec timeout - the Linux kernel uses the * same duration */ @@ -139,7 +139,7 @@ static int wait_for_ready(u8 *base) * is non-operative */ -static int wait_for_valid(u8 *base) +static int wait_for_valid(u32 base) { u32 reg32; @@ -163,7 +163,7 @@ static int wait_for_valid(u8 *base) return -1; } -static void codec_init(struct device *dev, u8 * base, int addr) +static void codec_init(struct device *dev, u32 base, int addr) { u32 reg32; u32 *verb; @@ -207,7 +207,7 @@ static void codec_init(struct device *dev, u8 * base, int addr) printk_debug("Azalia: verb loaded.\n"); } -static void codecs_init(struct device *dev, u8 * base, u32 codec_mask) +static void codecs_init(struct device *dev, u32 base, u32 codec_mask) { int i; for (i = 2; i >= 0; i--) { @@ -218,7 +218,7 @@ static void codecs_init(struct device *dev, u8 * base, u32 codec_mask) static void azalia_init(struct device *dev) { - u8 *base; + u32 base; struct resource *res; u32 codec_mask; u8 reg8; @@ -303,7 +303,7 @@ static void azalia_init(struct device *dev) // NOTE this will break as soon as the Azalia get's a bar above // 4G. Is there anything we can do about it? - base = (u8 *) ((u32)res->base); + base = (u32)res->base; printk_debug("Azalia: base = %08x\n", (u32)base); codec_mask = codec_detect(base); diff --git a/src/southbridge/intel/i82801gx/i82801gx_lpc.c b/src/southbridge/intel/i82801gx/i82801gx_lpc.c index be3eee68c5..ccab5482c9 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_lpc.c +++ b/src/southbridge/intel/i82801gx/i82801gx_lpc.c @@ -27,7 +27,6 @@ #include <pc80/i8259.h> #include <arch/io.h> #include "i82801gx.h" -#include "i82801gx_power.h" #define NMI_OFF 0 diff --git a/src/southbridge/intel/i82801gx/i82801gx_pci.c b/src/southbridge/intel/i82801gx/i82801gx_pci.c index 215563d9c2..d9057cb295 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_pci.c +++ b/src/southbridge/intel/i82801gx/i82801gx_pci.c @@ -22,6 +22,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include "i82801gx.h" static void pci_init(struct device *dev) { @@ -34,31 +35,31 @@ static void pci_init(struct device *dev) pci_write_config16(dev, PCI_COMMAND, reg16); /* This device has no interrupt */ - pci_write_config8(dev, 0x3c, 0xff); + pci_write_config8(dev, INTR, 0xff); /* disable parity error response and SERR */ - reg16 = pci_read_config16(dev, 0x3e); + reg16 = pci_read_config16(dev, BCTRL); reg16 &= ~(1 << 0); reg16 &= ~(1 << 1); - pci_write_config16(dev, 0x3e, reg16); + pci_write_config16(dev, BCTRL, reg16); /* Master Latency Count must be set to 0x04! */ - reg8 = pci_read_config8(dev, 0x1b); + reg8 = pci_read_config8(dev, SMLT); reg8 &= 0x07; reg8 |= (0x04 << 3); - pci_write_config8(dev, 0x1b, reg8); + pci_write_config8(dev, SMLT, reg8); /* Will this improve throughput of bus masters? */ pci_write_config8(dev, PCI_MIN_GNT, 0x06); /* Clear errors in status registers */ - reg16 = pci_read_config16(dev, 0x06); + reg16 = pci_read_config16(dev, PSTS); //reg16 |= 0xf900; - pci_write_config16(dev, 0x06, reg16); + pci_write_config16(dev, PSTS, reg16); - reg16 = pci_read_config16(dev, 0x1e); + reg16 = pci_read_config16(dev, SECSTS); // reg16 |= 0xf900; - pci_write_config16(dev, 0x1e, reg16); + pci_write_config16(dev, SECSTS, reg16); } #undef PCI_BRIDGE_UPDATE_COMMAND diff --git a/src/southbridge/intel/i82801gx/i82801gx_pcie.c b/src/southbridge/intel/i82801gx/i82801gx_pcie.c index 67120d6ded..b66a887063 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_pcie.c +++ b/src/southbridge/intel/i82801gx/i82801gx_pcie.c @@ -75,7 +75,7 @@ static void pci_init(struct device *dev) reg16 |= (1 << 6); pci_write_config16(dev, 0x50, reg16); -#if EVEN_MORE_DEBUG +#ifdef EVEN_MORE_DEBUG reg32 = pci_read_config32(dev, 0x20); printk_spew(" MBL = 0x%08x\n", reg32); reg32 = pci_read_config32(dev, 0x24); diff --git a/src/southbridge/intel/i82801gx/i82801gx_power.h b/src/southbridge/intel/i82801gx/i82801gx_power.h deleted file mode 100644 index ca72eb2831..0000000000 --- a/src/southbridge/intel/i82801gx/i82801gx_power.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define MAINBOARD_POWER_OFF 0 -#define MAINBOARD_POWER_ON 1 -#define MAINBOARD_POWER_KEEP 2 - -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - diff --git a/src/southbridge/intel/i82801gx/i82801gx_reset.c b/src/southbridge/intel/i82801gx/i82801gx_reset.c index 35710125b2..29b69ff43a 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_reset.c +++ b/src/southbridge/intel/i82801gx/i82801gx_reset.c @@ -19,6 +19,7 @@ */ #include <arch/io.h> +#include <reset.h> void soft_reset(void) { diff --git a/src/southbridge/intel/i82801gx/i82801gx_smi.c b/src/southbridge/intel/i82801gx/i82801gx_smi.c index 7187b1af91..0c70812412 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_smi.c +++ b/src/southbridge/intel/i82801gx/i82801gx_smi.c @@ -24,6 +24,7 @@ #include <device/pci.h> #include <console/console.h> #include <arch/io.h> +#include <cpu/cpu.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> #include <string.h> @@ -237,7 +238,7 @@ static void smi_set_eos(void) extern uint8_t smm_relocation_start, smm_relocation_end; -void smm_relocate(void) +static void smm_relocate(void) { u32 smi_en; u16 pm1_en; @@ -317,7 +318,7 @@ void smm_relocate(void) outb(0x00, 0xb2); } -void smm_install(void) +static void smm_install(void) { /* enable the SMM memory window */ pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, diff --git a/src/southbridge/intel/i82801gx/i82801gx_smihandler.c b/src/southbridge/intel/i82801gx/i82801gx_smihandler.c index cf44772d9f..2717dac2f8 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_smihandler.c +++ b/src/southbridge/intel/i82801gx/i82801gx_smihandler.c @@ -27,7 +27,6 @@ #include <cpu/x86/smm.h> #include <device/pci_def.h> #include "i82801gx.h" -#include "i82801gx_power.h" #define DEBUG_SMI diff --git a/src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c b/src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c index 9edee4faa8..3d61cae9b6 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c +++ b/src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c @@ -53,8 +53,8 @@ static void usb_ehci_init(struct device *dev) /* Clear any pending port changes */ res = find_resource(dev, 0x10); base = res->base; - reg32 = read32((u8 *)base + 0x24) | (1 << 2); - write32((u8 *)base + 0x24, reg32); + reg32 = read32(base + 0x24) | (1 << 2); + write32(base + 0x24, reg32); /* workaround */ reg8 = pci_read_config8(dev, 0x84); diff --git a/src/southbridge/intel/i82801gx/i82801gx_watchdog.c b/src/southbridge/intel/i82801gx/i82801gx_watchdog.c index 9304ffc705..38350d7ef2 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_watchdog.c +++ b/src/southbridge/intel/i82801gx/i82801gx_watchdog.c @@ -22,6 +22,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pci.h> +#include <watchdog.h> void watchdog_off(void) { |