diff options
Diffstat (limited to 'src/southbridge/intel/i82801ix/early_init.c')
| -rw-r--r-- | src/southbridge/intel/i82801ix/early_init.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index db17e73de9..18fe38b122 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -24,8 +24,7 @@ void i82801ix_early_init(void) /* Set up GPIOBASE. */ pci_write_config32(d31f0, D31F0_GPIO_BASE, DEFAULT_GPIOBASE); /* Enable GPIO. */ - pci_write_config8(d31f0, D31F0_GPIO_CNTL, - pci_read_config8(d31f0, D31F0_GPIO_CNTL) | 0x10); + pci_or_config8(d31f0, D31F0_GPIO_CNTL, 0x10); /* Reset watchdog. */ outw(0x0008, DEFAULT_TCOBASE + 0x04); /* R/WC, clear TCO caused SMI. */ @@ -40,6 +39,8 @@ void i82801ix_early_init(void) and 0xe (required if ME is disabled but present), bit 31 locks it. The other bits are 'must write'. */ u8 reg8 = pci_read_config8(d31f0, 0xac); + + /* FIXME: It's a 8-bit variable!!! */ reg8 |= (1 << 31) | (1 << 30) | (1 << 20) | (3 << 8); pci_write_config8(d31f0, 0xac, reg8); |