diff options
Diffstat (limited to 'src/southbridge/intel/i82801jx/early_init.c')
| -rw-r--r-- | src/southbridge/intel/i82801jx/early_init.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c index 8504c09bd0..8ed7a41784 100644 --- a/src/southbridge/intel/i82801jx/early_init.c +++ b/src/southbridge/intel/i82801jx/early_init.c @@ -59,9 +59,8 @@ void i82801jx_setup_bars(void) /* Set up GPIOBASE. */ pci_write_config32(d31f0, D31F0_GPIO_BASE, DEFAULT_GPIOBASE); - /* Enable GPIO. */ - pci_write_config8(d31f0, D31F0_GPIO_CNTL, - pci_read_config8(d31f0, D31F0_GPIO_CNTL) | 0x10); + /* Enable GPIO. */ + pci_or_config8(d31f0, D31F0_GPIO_CNTL, 0x10); } #define TCO_BASE 0x60 @@ -96,6 +95,8 @@ void i82801jx_early_init(void) and 0xe (required if ME is disabled but present), bit 31 locks it. The other bits are 'must write'. */ u8 reg8 = pci_read_config8(d31f0, 0xac); + + /* FIXME: It's a 8-bit variable!!! */ reg8 |= (1 << 31) | (1 << 30) | (1 << 20) | (3 << 8); pci_write_config8(d31f0, 0xac, reg8); |