diff options
Diffstat (limited to 'src/southbridge/intel/i82801jx')
| -rw-r--r-- | src/southbridge/intel/i82801jx/bootblock.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801jx/i82801jx.h | 1 |
2 files changed, 1 insertions, 2 deletions
diff --git a/src/southbridge/intel/i82801jx/bootblock.c b/src/southbridge/intel/i82801jx/bootblock.c index cc685c4544..911361af6b 100644 --- a/src/southbridge/intel/i82801jx/bootblock.c +++ b/src/southbridge/intel/i82801jx/bootblock.c @@ -34,6 +34,6 @@ static void bootblock_southbridge_init(void) enable_spi_prefetch(); /* Enable RCBA */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), D31F0_RCBA, + pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); } diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index 4813dd83b3..ad3b38177a 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -114,7 +114,6 @@ #define D31F0_CxSTATE_CNF 0xa9 #define D31F0_C4TIMING_CNT 0xaa #define D31F0_GPIO_ROUT 0xb8 -#define D31F0_RCBA 0xf0 /* GEN_PMCON_3 bits */ #define RTC_BATTERY_DEAD (1 << 2) |