diff options
Diffstat (limited to 'src/southbridge/intel/ibexpeak/lpc.c')
| -rw-r--r-- | src/southbridge/intel/ibexpeak/lpc.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 212471136d..db73b0add8 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -59,16 +59,16 @@ static void pch_enable_ioapic(struct device *dev) /* Enable ACPI I/O range decode */ pci_write_config8(dev, ACPI_CNTL, ACPI_EN); - set_ioapic_id(IO_APIC_ADDR, 0x01); + set_ioapic_id(VIO_APIC_VADDR, 0x01); /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read(IO_APIC_ADDR, 0x01); - io_apic_write(IO_APIC_ADDR, 0x01, reg32); + reg32 = io_apic_read(VIO_APIC_VADDR, 0x01); + io_apic_write(VIO_APIC_VADDR, 0x01, reg32); /* * Select Boot Configuration register (0x03) and * use Processor System Bus (0x01) to deliver interrupts. */ - io_apic_write(IO_APIC_ADDR, 0x03, 0x01); + io_apic_write(VIO_APIC_VADDR, 0x03, 0x01); } static void pch_enable_serial_irqs(struct device *dev) @@ -394,7 +394,7 @@ static void enable_hpet(void) reg32 &= ~(3 << 0); RCBA32(HPTC) = reg32; - write32(0xfed00010, read32(0xfed00010) | 1); + write32((u32 *)0xfed00010, read32((u32 *)0xfed00010) | 1); } static void enable_clock_gating(device_t dev) |