1 files changed, 48 insertions, 0 deletions
diff --git a/src/southbridge/intel/ich5r/ich5r.c b/src/southbridge/intel/ich5r/ich5r.c
new file mode 100644
index 0000000000..1b65465234
--- /dev/null
+++ b/src/southbridge/intel/ich5r/ich5r.c
@@ -0,0 +1,48 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "ich5r.h"
+
+void ich5r_enable(device_t dev)
+{
+	device_t lpc_dev;
+	unsigned index = 0;
+	uint16_t reg_old, reg;
+
+	/* See if we are on the behind the ich5r pci bridge */
+	lpc_dev = dev_find_slot(dev->bus->secondary, PCI_DEVFN(0x1f, 0));
+	if((dev->path.u.pci.devfn &0xf8)== 0xf8) {
+		index = dev->path.u.pci.devfn & 7;
+	}
+	else if((dev->path.u.pci.devfn &0xf8)== 0xe8) {
+		index = (dev->path.u.pci.devfn & 7) +8;
+	}
+	if ((!lpc_dev) || (index >= 16) || ((1<<index)&0x3091)) {
+		return;
+	}
+	if ((lpc_dev->vendor != PCI_VENDOR_ID_INTEL) ||
+		(lpc_dev->device != PCI_DEVICE_ID_INTEL_82801ER_ISA)) {
+		uint32_t id;
+		id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
+		if (id != (PCI_VENDOR_ID_INTEL | 
+				(PCI_DEVICE_ID_INTEL_82801ER_ISA << 16))) {
+			return;
+		}
+	}
+
+	reg = reg_old = pci_read_config16(lpc_dev, 0xf2);
+	reg &= ~(1 << index);
+	if (!dev->enabled) {
+		reg |= (1 << index);
+	}
+	if (reg != reg_old) {
+		pci_write_config16(lpc_dev, 0xf2, reg);
+	}
+	
+}
+
+struct chip_operations southbridge_intel_ich5r_ops = {
+	CHIP_NAME("INTEL 82801ER")
+	.enable_dev = ich5r_enable,
+};