18 files changed, 148 insertions, 70 deletions

diff --git a/src/southbridge/intel/ich5r/Config.lb b/src/southbridge/intel/ich5r/Config.lb
index 0bad3f0bf5..1953eaabdf 100644
--- a/src/southbridge/intel/ich5r/Config.lb
+++ b/src/southbridge/intel/ich5r/Config.lb
@@ -1,11 +1,12 @@
 config chip.h
-driver ich5r.o
-driver ich5r_uhci.o
-driver ich5r_lpc.o
-driver ich5r_ide.o
-driver ich5r_sata.o
-driver ich5r_ehci.o
-driver ich5r_smbus.o
-driver ich5r_pci.o
-driver ich5r_ac97.o
-object ich5r_watchdog.o
+driver i82801er.o
+driver i82801er_uhci.o
+driver i82801er_lpc.o
+driver i82801er_ide.o
+driver i82801er_sata.o
+driver i82801er_ehci.o
+driver i82801er_smbus.o
+driver i82801er_pci.o
+driver i82801er_ac97.o
+object i82801er_watchdog.o
+object i82801er_reset.o
diff --git a/src/southbridge/intel/ich5r/chip.h b/src/southbridge/intel/ich5r/chip.h
index b3abeabca7..eb63889794 100644
--- a/src/southbridge/intel/ich5r/chip.h
+++ b/src/southbridge/intel/ich5r/chip.h
@@ -1,4 +1,7 @@
-struct southbridge_intel_ich5r_config 
+#ifndef I82801ER_CHIP_H
+#define I82801ER_CHIP_H
+
+struct southbridge_intel_i82801er_config 
 {
 
 #define ICH5R_GPIO_USE_MASK      0x03
@@ -27,4 +30,7 @@ struct southbridge_intel_ich5r_config
 	unsigned int  pirq_a_d;
 	unsigned int  pirq_e_h;
 };
-extern struct chip_operations southbridge_intel_ich5r_ops;
+extern struct chip_operations southbridge_intel_i82801er_ops;
+
+#endif /* I82801ER_CHIP_H */
+
diff --git a/src/southbridge/intel/ich5r/cmos_failover.c b/src/southbridge/intel/ich5r/cmos_failover.c
new file mode 100644
index 0000000000..9702313f9c
--- /dev/null
+++ b/src/southbridge/intel/ich5r/cmos_failover.c
@@ -0,0 +1,16 @@
+//kind of cmos_err for ich5
+#define RTC_FAILED    (1 <<2)
+#define GEN_PMCON_3     0xa4
+static void check_cmos_failed(void) 
+{
+
+                uint8_t byte;
+                byte = pci_read_config8(PCI_DEV(0,0x1f,0),GEN_PMCON_3);
+                if( byte & RTC_FAILED){
+//clear bit 1 and bit 2
+                        byte = cmos_read(RTC_BOOT_BYTE);
+                        byte &= 0x0c;
+                        byte |= MAX_REBOOT_CNT << 4;
+                        cmos_write(byte, RTC_BOOT_BYTE);
+                }
+}
diff --git a/src/southbridge/intel/ich5r/ich5r.c b/src/southbridge/intel/ich5r/i82801er.c
index 1b65465234..5e38ac3acb 100644
--- a/src/southbridge/intel/ich5r/ich5r.c
+++ b/src/southbridge/intel/ich5r/i82801er.c
@@ -2,15 +2,15 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include "ich5r.h"
+#include "i82801er.h"
 
-void ich5r_enable(device_t dev)
+void i82801er_enable(device_t dev)
 {
 	device_t lpc_dev;
 	unsigned index = 0;
 	uint16_t reg_old, reg;
 
-	/* See if we are on the behind the ich5r pci bridge */
+	/* See if we are behind the i82801er pci bridge */
 	lpc_dev = dev_find_slot(dev->bus->secondary, PCI_DEVFN(0x1f, 0));
 	if((dev->path.u.pci.devfn &0xf8)== 0xf8) {
 		index = dev->path.u.pci.devfn & 7;
@@ -42,7 +42,7 @@ void ich5r_enable(device_t dev)
 	
 }
 
-struct chip_operations southbridge_intel_ich5r_ops = {
-	CHIP_NAME("INTEL 82801ER")
-	.enable_dev = ich5r_enable,
+struct chip_operations southbridge_intel_i82801er_ops = {
+	CHIP_NAME("Intel 82801ER Southbridge")
+	.enable_dev = i82801er_enable,
 };
diff --git a/src/southbridge/intel/ich5r/i82801er.h b/src/southbridge/intel/ich5r/i82801er.h
new file mode 100644
index 0000000000..bd7410162b
--- /dev/null
+++ b/src/southbridge/intel/ich5r/i82801er.h
@@ -0,0 +1,15 @@
+#ifndef I82801ER_H
+#define I82801ER_H
+
+#include "chip.h"
+
+extern void i82801er_enable(device_t dev);
+
+#define PCI_DMA_CFG     0x90
+#define SERIRQ_CNTL     0x64
+#define GEN_CNTL        0xd0
+#define GEN_STS         0xd4
+#define RTC_CONF        0xd8
+#define GEN_PMCON_3     0xa4
+
+#endif /* I82801ER_H */
diff --git a/src/southbridge/intel/ich5r/ich5r_ac97.c b/src/southbridge/intel/ich5r/i82801er_ac97.c
index 17d924b196..ffc062e718 100644
--- a/src/southbridge/intel/ich5r/ich5r_ac97.c
+++ b/src/southbridge/intel/ich5r/i82801er_ac97.c
@@ -3,7 +3,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
-#include "ich5r.h"
+#include "i82801er.h"
 
 static void ac97_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
@@ -21,7 +21,7 @@ static struct device_operations ac97_ops  = {
 	.enable_resources = pci_dev_enable_resources,
 	.init             = 0,
 	.scan_bus         = 0,
-	.enable           = ich5r_enable,
+	.enable           = i82801er_enable,
 	.ops_pci          = &lops_pci,
 };
 
diff --git a/src/southbridge/intel/ich5r/ich5r_early_smbus.c b/src/southbridge/intel/ich5r/i82801er_early_smbus.c
index 6880fde126..ef40e16b9f 100644
--- a/src/southbridge/intel/ich5r/ich5r_early_smbus.c
+++ b/src/southbridge/intel/ich5r/i82801er_early_smbus.c
@@ -1,4 +1,4 @@
-#include "ich5r_smbus.h"
+#include "i82801er_smbus.h"
 
 #define SMBUS_IO_BASE 0x0f00
 
@@ -9,10 +9,12 @@ static void enable_smbus(void)
 	if (dev == PCI_DEV_INVALID) {
 		die("SMBUS controller not found\r\n");
 	}
-	uint8_t enable;
 	print_spew("SMBus controller enabled\r\n");
+	
 	pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
+	/* Set smbus enable */
 	pci_write_config8(dev, 0x40, 1);
+	/* Set smbus iospace enable */
 	pci_write_config8(dev, 0x4, 1);
 	/* SMBALERT_DIS */
 	pci_write_config8(dev, 0x11, 4);
@@ -20,10 +22,15 @@ static void enable_smbus(void)
 	/* Disable interrupt generation */
 	outb(0, SMBUS_IO_BASE + SMBHSTCTL);
 
+	/* clear any lingering errors, so the transaction will run */
+	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
+
+#if 0	// It's unlikely that half the southbridge suddenly vanishes?
 	dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
 	if (dev == PCI_DEV_INVALID) {
 		die("ISA bridge not found\r\n");
 	}
+#endif
 }
 
 static int smbus_read_byte(unsigned device, unsigned address)
@@ -36,6 +43,9 @@ static void smbus_write_byte(unsigned device, unsigned address, unsigned char va
 	if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) {
 		return;
 	}
+	
+	print_debug("Unimplemented smbus_write_byte() called.\r\n");
+
 #if 0
 	/* setup transaction */
 	/* disable interrupts */
diff --git a/src/southbridge/intel/ich5r/ich5r_ehci.c b/src/southbridge/intel/ich5r/i82801er_ehci.c
index d1650c1385..c7a291233f 100644
--- a/src/southbridge/intel/ich5r/ich5r_ehci.c
+++ b/src/southbridge/intel/ich5r/i82801er_ehci.c
@@ -3,7 +3,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
-#include "ich5r.h"
+#include "i82801er.h"
 
 static void ehci_init(struct device *dev)
 {
@@ -39,7 +39,7 @@ static struct device_operations ehci_ops  = {
 	.enable_resources = pci_dev_enable_resources,
 	.init             = ehci_init,
 	.scan_bus         = 0,
-	.enable           = ich5r_enable,
+	.enable           = i82801er_enable,
 	.ops_pci          = &lops_pci,
 };
 
diff --git a/src/southbridge/intel/ich5r/ich5r_ide.c b/src/southbridge/intel/ich5r/i82801er_ide.c
index 7bfd92555c..e42f775029 100644
--- a/src/southbridge/intel/ich5r/ich5r_ide.c
+++ b/src/southbridge/intel/ich5r/i82801er_ide.c
@@ -3,21 +3,20 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
-#include "ich5r.h"
+#include "i82801er.h"
 
 static void ide_init(struct device *dev)
 {
-
 	/* Enable IDE devices and timmings */
-	pci_write_config16(dev, 0x40, 0x0a307);
-	pci_write_config16(dev, 0x42, 0x0a307);
+	pci_write_config16(dev, 0x40, 0x0a307); // IDE0
+	pci_write_config16(dev, 0x42, 0x0a307); // IDE1
 	pci_write_config8(dev, 0x48, 0x05);
 	pci_write_config16(dev, 0x4a, 0x0101);
 	pci_write_config16(dev, 0x54, 0x5055);
 	printk_debug("IDE Enabled\n");
 }
 
-static void ich5r_ide_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void i82801er_ide_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
 	/* This value is also visible in uchi[0-2] and smbus functions */
 	pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, 
@@ -25,7 +24,7 @@ static void ich5r_ide_set_subsystem(device_t dev, unsigned vendor, unsigned devi
 }
 
 static struct pci_operations lops_pci = {
-	.set_subsystem = ich5r_ide_set_subsystem,
+	.set_subsystem = i82801er_ide_set_subsystem,
 };
 static struct device_operations ide_ops  = {
 	.read_resources   = pci_dev_read_resources,
diff --git a/src/southbridge/intel/ich5r/ich5r_lpc.c b/src/southbridge/intel/ich5r/i82801er_lpc.c
index d9d98891ad..3f77b51409 100644
--- a/src/southbridge/intel/ich5r/ich5r_lpc.c
+++ b/src/southbridge/intel/ich5r/i82801er_lpc.c
@@ -9,7 +9,7 @@
 #include <pc80/mc146818rtc.h>
 #include <pc80/isa-dma.h>
 #include <arch/io.h>
-#include "ich5r.h"
+#include "i82801er.h"
 
 #define ACPI_BAR 0x40
 #define GPIO_BAR 0x58
@@ -68,7 +68,7 @@ static void setup_ioapic(void)
 }
 
 #define SERIRQ_CNTL 0x64
-static void ich5r_enable_serial_irqs(device_t dev)
+static void i82801er_enable_serial_irqs(device_t dev)
 {
 	/* set packet length and toggle silent mode bit */
 	pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0));
@@ -76,22 +76,22 @@ static void ich5r_enable_serial_irqs(device_t dev)
 }
 
 #define PCI_DMA_CFG 0x90
-static void ich5r_pci_dma_cfg(device_t dev)
+static void i82801er_pci_dma_cfg(device_t dev)
 {
 	/* Set PCI DMA CFG to lpc I/F DMA */
 	pci_write_config16(dev, PCI_DMA_CFG, 0xfcff);
 }
 
 #define LPC_EN 0xe6
-static void ich5r_enable_lpc(device_t dev)
+static void i82801er_enable_lpc(device_t dev)
 {
         /* lpc i/f enable */
         pci_write_config8(dev, LPC_EN, 0x0d);
 }
 
-typedef struct southbridge_intel_ich5r_config config_t;
+typedef struct southbridge_intel_i82801er_config config_t;
 
-static void set_ich5r_gpio_use_sel(
+static void set_i82801er_gpio_use_sel(
 	device_t dev, struct resource *res, config_t *config)
 {
 	uint32_t gpio_use_sel, gpio_use_sel2;
@@ -120,7 +120,7 @@ static void set_ich5r_gpio_use_sel(
 	outl(gpio_use_sel2, res->base + 0x30);
 }
 
-static void set_ich5r_gpio_direction(
+static void set_i82801er_gpio_direction(
 	device_t dev, struct resource *res, config_t *config)
 {
 	uint32_t gpio_io_sel, gpio_io_sel2;
@@ -149,7 +149,7 @@ static void set_ich5r_gpio_direction(
 	outl(gpio_io_sel2, res->base + 0x34);
 }
 
-static void set_ich5r_gpio_level(
+static void set_i82801er_gpio_level(
 	device_t dev, struct resource *res, config_t *config)
 {
 	uint32_t gpio_lvl, gpio_lvl2;
@@ -184,7 +184,7 @@ static void set_ich5r_gpio_level(
 	outl(gpio_lvl2,  res->base + 0x38);
 }
 
-static void set_ich5r_gpio_inv(
+static void set_i82801er_gpio_inv(
 	device_t dev, struct resource *res, config_t *config)
 {
 	uint32_t gpio_inv;
@@ -205,7 +205,7 @@ static void set_ich5r_gpio_inv(
 	outl(gpio_inv,   res->base + 0x2c);
 }
 
-static void ich5r_pirq_init(device_t dev)
+static void i82801er_pirq_init(device_t dev)
 {
 	config_t *config;
 
@@ -221,7 +221,7 @@ static void ich5r_pirq_init(device_t dev)
 }
 
 
-static void ich5r_gpio_init(device_t dev)
+static void i82801er_gpio_init(device_t dev)
 {
 	struct resource *res;
 	config_t *config;
@@ -243,19 +243,41 @@ static void ich5r_gpio_init(device_t dev)
 	}
 
 	/* Set the use selects */
-	set_ich5r_gpio_use_sel(dev, res, config);
+	set_i82801er_gpio_use_sel(dev, res, config);
 
 	/* Set the IO direction */
-	set_ich5r_gpio_direction(dev, res, config);
+	set_i82801er_gpio_direction(dev, res, config);
 
 	/* Setup the input inverters */
-	set_ich5r_gpio_inv(dev, res, config);
+	set_i82801er_gpio_inv(dev, res, config);
 
 	/* Set the value on the GPIO output pins */
-	set_ich5r_gpio_level(dev, res, config);
+	set_i82801er_gpio_level(dev, res, config);
 
 }
 
+static void enable_hpet(struct device *dev)
+{
+const unsigned long hpet_address = 0xfed0000;
+
+	uint32_t dword;
+	uint32_t code = (0 & 0x3);
+
+	dword = pci_read_config32(dev, GEN_CNTL);
+	dword |= (1 << 17); /* enable hpet */
+
+	/* Bits [16:15]  Memory Address Range
+	 *	    00   FED0_0000h - FED0_03FFh
+	 *	    01   FED0_1000h - FED0_13FFh
+	 *	    10   FED0_2000h - FED0_23FFh
+	 *	    11   FED0_3000h - FED0_33FFh
+	 */
+
+	dword &= ~(3 << 15); /* clear it */
+	dword |= (code<<15);
+
+	printk_debug("enabling HPET @0x%x\n", hpet_address | (code <<12) );
+}
 
 static void lpc_init(struct device *dev)
 {
@@ -272,11 +294,11 @@ static void lpc_init(struct device *dev)
 	pci_write_config32(dev, 0xd4, value);
 	setup_ioapic();
 
-	ich5r_enable_serial_irqs(dev);
+	i82801er_enable_serial_irqs(dev);
 
-	ich5r_pci_dma_cfg(dev);
+	i82801er_pci_dma_cfg(dev);
 
-	ich5r_enable_lpc(dev);
+	i82801er_enable_lpc(dev);
 
 	/* Clear SATA to non raid */
 	pci_write_config8(dev, 0xae, 0x00);
@@ -291,10 +313,10 @@ static void lpc_init(struct device *dev)
 	printk_info("set power %s after power fail\n", pwr_on?"on":"off");
 
 	/* Set up the PIRQ */
-	ich5r_pirq_init(dev);
+	i82801er_pirq_init(dev);
 	
 	/* Set the state of the gpio lines */
-	ich5r_gpio_init(dev);
+	i82801er_gpio_init(dev);
 
 	/* Initialize the real time clock */
 	rtc_init(0);
@@ -305,9 +327,10 @@ static void lpc_init(struct device *dev)
 	/* Disable IDE (needed when sata is enabled) */
 	pci_write_config8(dev, 0xf2, 0x60);
 	
+	enable_hpet(dev);
 }
 
-static void ich5r_lpc_read_resources(device_t dev)
+static void i82801er_lpc_read_resources(device_t dev)
 {
 	struct resource *res;
 
@@ -328,7 +351,7 @@ static void ich5r_lpc_read_resources(device_t dev)
 	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 }
 
-static void ich5r_lpc_enable_resources(device_t dev)
+static void i82801er_lpc_enable_resources(device_t dev)
 {
 	uint8_t acpi_cntl, gpio_cntl;
 
@@ -353,12 +376,12 @@ static struct pci_operations lops_pci = {
 };
 
 static struct device_operations lpc_ops  = {
-	.read_resources   = ich5r_lpc_read_resources,
+	.read_resources   = i82801er_lpc_read_resources,
 	.set_resources    = pci_dev_set_resources,
-	.enable_resources = ich5r_lpc_enable_resources,
+	.enable_resources = i82801er_lpc_enable_resources,
 	.init             = lpc_init,
 	.scan_bus         = scan_static_bus,
-	.enable           = ich5r_enable,
+	.enable           = i82801er_enable,
 	.ops_pci          = &lops_pci,
 };
 
diff --git a/src/southbridge/intel/ich5r/ich5r_pci.c b/src/southbridge/intel/ich5r/i82801er_pci.c
index d2c94c778e..c0b6aa9ad3 100644
--- a/src/southbridge/intel/ich5r/ich5r_pci.c
+++ b/src/southbridge/intel/ich5r/i82801er_pci.c
@@ -3,11 +3,11 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
-#include "ich5r.h"
+#include "i82801er.h"
 
 static void pci_init(struct device *dev)
 {
-
+	uint32_t dword;
 	uint16_t word;
 
 	/* Clear system errors */
@@ -15,6 +15,14 @@ static void pci_init(struct device *dev)
 	word |= 0xf900; /* Clear possible errors */
 	pci_write_config16(dev, 0x06, word);
 
+#if 0
+	/* System error enable */
+	dword = pci_read_config32(dev, 0x04);
+	dword |= (1<<8); /* SERR# Enable */
+	dword |= (1<<6); /* Parity Error Response */
+	pci_write_config32(dev, 0x04, dword);
+#endif				
+	
 	word = pci_read_config16(dev, 0x1e);
 	word |= 0xf800; /* Clear possible errors */
 	pci_write_config16(dev, 0x1e, word);
diff --git a/src/southbridge/intel/ich5r/i82801er_reset.c b/src/southbridge/intel/ich5r/i82801er_reset.c
new file mode 100644
index 0000000000..fa41756557
--- /dev/null
+++ b/src/southbridge/intel/ich5r/i82801er_reset.c
@@ -0,0 +1,7 @@
+#include <arch/io.h>
+
+void i82801er_hard_reset(void)
+{
+        /* Try rebooting through port 0xcf9 */
+        outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
+}
diff --git a/src/southbridge/intel/ich5r/ich5r_sata.c b/src/southbridge/intel/ich5r/i82801er_sata.c
index 803d8789cf..d9eba3c5a1 100644
--- a/src/southbridge/intel/ich5r/ich5r_sata.c
+++ b/src/southbridge/intel/ich5r/i82801er_sata.c
@@ -3,7 +3,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
-#include "ich5r.h"
+#include "i82801er.h"
 
 static void sata_init(struct device *dev)
 {
diff --git a/src/southbridge/intel/ich5r/ich5r_smbus.c b/src/southbridge/intel/ich5r/i82801er_smbus.c
index 3337a65b15..67bdd8722c 100644
--- a/src/southbridge/intel/ich5r/ich5r_smbus.c
+++ b/src/southbridge/intel/ich5r/i82801er_smbus.c
@@ -5,8 +5,8 @@
 #include <device/pci_ops.h>
 #include <device/smbus.h>
 #include <arch/io.h>
-#include "ich5r.h"
-#include "ich5r_smbus.h"
+#include "i82801er.h"
+#include "i82801er_smbus.h"
 
 static int lsmbus_read_byte(struct bus *bus, device_t dev, uint8_t address)
 {
@@ -32,7 +32,7 @@ static struct device_operations smbus_ops = {
 	.enable_resources = pci_dev_enable_resources,
 	.init             = 0,
 	.scan_bus         = scan_static_bus,
-	.enable           = ich5r_enable,
+	.enable           = i82801er_enable,
 	.ops_pci          = &lops_pci,
 	.ops_smbus_bus    = &lops_smbus_bus,
 };
diff --git a/src/southbridge/intel/ich5r/ich5r_smbus.h b/src/southbridge/intel/ich5r/i82801er_smbus.h
index 861230e130..861230e130 100644
--- a/src/southbridge/intel/ich5r/ich5r_smbus.h
+++ b/src/southbridge/intel/ich5r/i82801er_smbus.h
diff --git a/src/southbridge/intel/ich5r/ich5r_uhci.c b/src/southbridge/intel/ich5r/i82801er_uhci.c
index ad4ae978cf..733acb7410 100644
--- a/src/southbridge/intel/ich5r/ich5r_uhci.c
+++ b/src/southbridge/intel/ich5r/i82801er_uhci.c
@@ -3,7 +3,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
-#include "ich5r.h"
+#include "i82801er.h"
 
 static void uhci_init(struct device *dev)
 {
@@ -32,7 +32,7 @@ static struct device_operations uhci_ops  = {
 	.enable_resources = pci_dev_enable_resources,
 	.init             = uhci_init,
 	.scan_bus         = 0,
-	.enable           = ich5r_enable,
+	.enable           = i82801er_enable,
 	.ops_pci          = &lops_pci,
 };
 
diff --git a/src/southbridge/intel/ich5r/ich5r_watchdog.c b/src/southbridge/intel/ich5r/i82801er_watchdog.c
index c9c09f5896..c9c09f5896 100644
--- a/src/southbridge/intel/ich5r/ich5r_watchdog.c
+++ b/src/southbridge/intel/ich5r/i82801er_watchdog.c
diff --git a/src/southbridge/intel/ich5r/ich5r.h b/src/southbridge/intel/ich5r/ich5r.h
deleted file mode 100644
index 28572c9c27..0000000000
--- a/src/southbridge/intel/ich5r/ich5r.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef ICH5R_H
-#define ICH5R_H
-
-#include "chip.h"
-void ich5r_enable(device_t dev);
-
-#endif /* ICH5R_H */