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Diffstat (limited to 'src/southbridge/intel/lynxpoint/chip.h')
-rw-r--r--src/southbridge/intel/lynxpoint/chip.h10
1 files changed, 6 insertions, 4 deletions
diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h
index e30d4b4c21..40d0460419 100644
--- a/src/southbridge/intel/lynxpoint/chip.h
+++ b/src/southbridge/intel/lynxpoint/chip.h
@@ -47,7 +47,8 @@ struct southbridge_intel_lynxpoint_config {
uint32_t sata_port0_gen3_dtle;
uint32_t sata_port1_gen3_dtle;
- /* SATA DEVSLP Mux
+ /*
+ * SATA DEVSLP Mux
* 0 = port 0 DEVSLP on DEVSLP0/GPIO33
* 1 = port 3 DEVSLP on DEVSLP0/GPIO33
*/
@@ -67,12 +68,13 @@ struct southbridge_intel_lynxpoint_config {
/* Enable linear PCIe Root Port function numbers starting at zero */
uint8_t pcie_port_coalesce;
+
/* Force root port ASPM configuration with port bitmap */
uint8_t pcie_port_force_aspm;
- /* Serial IO configuration */
- /* Put devices into ACPI mode instead of a PCI device */
+ /* Put SerialIO devices into ACPI mode instead of a PCI device */
uint8_t sio_acpi_mode;
+
/* I2C voltage select: 0=3.3V 1=1.8V */
uint8_t sio_i2c0_voltage;
uint8_t sio_i2c1_voltage;
@@ -91,4 +93,4 @@ struct southbridge_intel_lynxpoint_config {
bool docking_supported;
};
-#endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H */
+#endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H */