summaryrefslogtreecommitdiff
path: root/src/southbridge/intel/lynxpoint/me_9.x.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/southbridge/intel/lynxpoint/me_9.x.c')
-rw-r--r--src/southbridge/intel/lynxpoint/me_9.x.c8
1 files changed, 2 insertions, 6 deletions
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c
index 9910658b82..69192e6ccb 100644
--- a/src/southbridge/intel/lynxpoint/me_9.x.c
+++ b/src/southbridge/intel/lynxpoint/me_9.x.c
@@ -25,10 +25,7 @@
#include "me.h"
#include "pch.h"
-#if CONFIG(CHROMEOS)
#include <vendorcode/google/chromeos/chromeos.h>
-#include <vendorcode/google/chromeos/gnvs.h>
-#endif
/* Path that the BIOS should take based on ME state */
static const char *const me_bios_path_values[] __unused = {
@@ -755,10 +752,9 @@ static int intel_me_extend_valid(struct device *dev)
}
printk(BIOS_DEBUG, "\n");
-#if CONFIG(CHROMEOS)
/* Save hash in NVS for the OS to verify */
- chromeos_set_me_hash(extend, count);
-#endif
+ if (CONFIG(CHROMEOS))
+ chromeos_set_me_hash(extend, count);
return 0;
}