diff options
Diffstat (limited to 'src/southbridge/intel/lynxpoint/me_9.x.c')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/me_9.x.c | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index facfc37645..12f7ab7ed2 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -39,7 +39,6 @@ #ifdef __SMM__ # include <arch/romcc_io.h> -# include <northbridge/intel/haswell/pcie_config.c> #else # include <device/device.h> # include <device/pci.h> @@ -496,14 +495,14 @@ void intel_me_finalize_smm(void) u32 reg32; mei_base_address = - pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf; + pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf; /* S3 path will have hidden this device already */ if (!mei_base_address || mei_base_address == 0xfffffff0) return; /* Make sure ME is in a mode that expects EOP */ - reg32 = pcie_read_config32(PCH_ME_DEV, PCI_ME_HFS); + reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); memcpy(&hfs, ®32, sizeof(u32)); /* Abort and leave device alone if not normal mode */ @@ -516,10 +515,10 @@ void intel_me_finalize_smm(void) mkhi_end_of_post(); /* Make sure IO is disabled */ - reg32 = pcie_read_config32(PCH_ME_DEV, PCI_COMMAND); + reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND); reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pcie_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); + pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); /* Hide the PCI device */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); |