summaryrefslogtreecommitdiff
path: root/src/southbridge/intel/lynxpoint/pch.h
diff options
context:
space:
mode:
Diffstat (limited to 'src/southbridge/intel/lynxpoint/pch.h')
-rw-r--r--src/southbridge/intel/lynxpoint/pch.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index d76faf74dd..655aef1353 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -242,7 +242,7 @@ void pch_enable_lpc(void);
#define GEN_PMCON_2 0xa2
#define GEN_PMCON_3 0xa4
#define PMIR 0xac
-#define PMIR_CF9LOCK (1 << 31)
+#define PMIR_CF9LOCK (1UL << 31)
#define PMIR_CF9GR (1 << 20)
/* GEN_PMCON_3 bits */
@@ -389,7 +389,7 @@ void pch_enable_lpc(void);
#define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */
#define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */
#define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */
-#define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */
+#define XHCI_USB3_PORTSC_WPR (1UL << 31) /* Warm Port Reset */
#define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */
#define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */
#define XHCI_PLSR_RXDETECT (5 << 5) /* Port is disconnected */