diff options
Diffstat (limited to 'src/southbridge/intel/lynxpoint')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/bootblock.c | 14 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/early_pch.c | 11 |
2 files changed, 0 insertions, 25 deletions
diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 1a9e7bba61..cb595cdd0c 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -14,20 +14,8 @@ */ #include <arch/io.h> -#include <cpu/x86/tsc.h> #include "pch.h" -static void store_initial_timestamp(void) -{ - /* On Cougar Point we have two 32bit scratchpad registers available: - * D0:F0 0xdc (SKPAD) - * D31:F2 0xd0 (SATA SP) - */ - tsc_t tsc = rdtsc(); - pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo); - pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi); -} - /* * Enable Prefetching and Caching. */ @@ -83,8 +71,6 @@ static void set_spi_speed(void) static void bootblock_southbridge_init(void) { - store_initial_timestamp(); - map_rcba(); enable_spi_prefetch(); enable_port80_on_lpc(); diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 46e803d82f..912df8ea4c 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -18,8 +18,6 @@ #include <arch/io.h> #include <device/device.h> #include <device/pci_def.h> -#include <timestamp.h> -#include <cpu/x86/tsc.h> #include <elog.h> #include "pch.h" #include "chip.h" @@ -68,15 +66,6 @@ static void pch_generic_setup(void) printk(BIOS_DEBUG, " done.\n"); } -uint64_t get_initial_timestamp(void) -{ - tsc_t base_time = { - .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), - .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) - }; - return tsc_to_uint64(base_time); -} - static int sleep_type_s3(void) { u32 pm1_cnt; |