diff options
Diffstat (limited to 'src/southbridge/intel/lynxpoint')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/acpi/pch.asl | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/early_pch.c | 6 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/lpc.c | 8 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/me_9.x.c | 22 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pch.h | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pmutil.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/smi.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/smihandler.c | 10 |
8 files changed, 28 insertions, 28 deletions
diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index a25282a390..90ff02d1f1 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -96,7 +96,7 @@ Scope(\) #include "smbus.asl" // Serial IO -#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP) +#if CONFIG(INTEL_LYNXPOINT_LP) #include "serialio.asl" #include "lpt_lp.asl" #endif diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index a5c69e050c..994021c6b0 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -23,7 +23,7 @@ #include "pch.h" #include "chip.h" -#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP) +#if CONFIG(INTEL_LYNXPOINT_LP) #include "lp_gpio.h" #else #include <southbridge/intel/common/gpio.h> @@ -127,7 +127,7 @@ int early_pch_init(const void *gpio_map, pch_enable_bars(); -#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP) +#if CONFIG(INTEL_LYNXPOINT_LP) setup_pch_lp_gpios(gpio_map); #else setup_pch_gpios(gpio_map); @@ -150,7 +150,7 @@ int early_pch_init(const void *gpio_map, wake_from_s3 = sleep_type_s3(); -#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) +#if CONFIG(ELOG_BOOT_COUNT) if (!wake_from_s3) boot_count_increment(); #endif diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 59074e09e6..94b3111d1e 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -82,7 +82,7 @@ static void pch_enable_serial_irqs(struct device *dev) /* Set packet length and toggle silent mode bit for one frame. */ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); -#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) +#if !CONFIG(SERIRQ_CONTINUOUS_MODE) pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); #endif @@ -490,7 +490,7 @@ static void enable_lp_clock_gating(struct device *dev) static void pch_set_acpi_mode(void) { -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) if (!acpi_is_wakeup_s3()) { #if ENABLE_ACPI_MODE_IN_COREBOOT printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); @@ -754,7 +754,7 @@ static void southbridge_inject_dsdt(struct device *dev) gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->pcnt = dev_count_cpu(); -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) chromeos_init_chromeos_acpi(&(gnvs->chromeos)); #endif @@ -976,7 +976,7 @@ static void lpc_final(struct device *dev) RCBA32(0x3898) = SPI_OPMENU_LOWER; RCBA32(0x389c) = SPI_OPMENU_UPPER; - if (acpi_is_wakeup_s3() || IS_ENABLED(CONFIG_INTEL_CHIPSET_LOCKDOWN)) + if (acpi_is_wakeup_s3() || CONFIG(INTEL_CHIPSET_LOCKDOWN)) outb(APM_CNT_FINALIZE, APM_CNT); } diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 450091c623..f5f94fe625 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -38,7 +38,7 @@ #include "me.h" #include "pch.h" -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -64,7 +64,7 @@ void intel_me_mbp_clear(pci_devfn_t dev); void intel_me_mbp_clear(struct device *dev); #endif -#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) +#if CONFIG(DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; @@ -378,7 +378,7 @@ static int mei_recv_msg(void *header, int header_bytes, return mei_wait_for_me_ready(); } -#if IS_ENABLED (CONFIG_DEBUG_INTEL_ME) || defined(__SMM__) +#if CONFIG(DEBUG_INTEL_ME) || defined(__SMM__) static inline int mei_sendrecv_mkhi(struct mkhi_header *mkhi, void *req_data, int req_bytes, void *rsp_data, int rsp_bytes) @@ -480,7 +480,7 @@ static void me_print_fw_version(mbp_fw_version_name *vers_name) vers_name->hotfix_version, vers_name->build_version); } -#if IS_ENABLED (CONFIG_DEBUG_INTEL_ME) +#if CONFIG(DEBUG_INTEL_ME) static inline void print_cap(const char *name, int state) { printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", @@ -536,7 +536,7 @@ static void me_print_fwcaps(mbp_mefwcaps *cap) #endif /* CONFIG_DEBUG_INTEL_ME */ #endif -#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */ +#if CONFIG(CHROMEOS) && 0 /* DISABLED */ /* Tell ME to issue a global reset */ static int mkhi_global_reset(void) { @@ -596,7 +596,7 @@ void intel_me_finalize_smm(void) if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0) return; -#if IS_ENABLED(CONFIG_ME_MBP_CLEAR_LATE) +#if CONFIG(ME_MBP_CLEAR_LATE) /* Wait for ME MBP Cleared indicator */ intel_me_mbp_clear(PCH_ME_DEV); #endif @@ -723,7 +723,7 @@ static me_bios_path intel_me_path(struct device *dev) path = ME_ERROR_BIOS_PATH; } -#if IS_ENABLED(CONFIG_ELOG) +#if CONFIG(ELOG) if (path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, @@ -812,7 +812,7 @@ static int intel_me_extend_valid(struct device *dev) } printk(BIOS_DEBUG, "\n"); -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) /* Save hash in NVS for the OS to verify */ chromeos_set_me_hash(extend, count); #endif @@ -851,7 +851,7 @@ static void intel_me_init(struct device *dev) #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) me_print_fw_version(mbp_data.fw_version_name); -#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) +#if CONFIG(DEBUG_INTEL_ME) me_print_fwcaps(mbp_data.fw_capabilities); #endif @@ -1008,7 +1008,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) host.interrupt_generate = 1; write_host_csr(&host); -#if !IS_ENABLED(CONFIG_ME_MBP_CLEAR_LATE) +#if !CONFIG(ME_MBP_CLEAR_LATE) /* Wait for the mbp_cleared indicator. */ intel_me_mbp_clear(dev); #endif @@ -1017,7 +1017,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", mbp->header.num_entries, mbp->header.mbp_size); -#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) +#if CONFIG(DEBUG_INTEL_ME) for (i = 0; i < mbp->header.mbp_size - 1; i++) { printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]); } diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 026fcdd383..97d0aa33b3 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -72,7 +72,7 @@ #define SMBUS_IO_BASE 0x0400 #define SMBUS_SLAVE_ADDR 0x24 -#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP) +#if CONFIG(INTEL_LYNXPOINT_LP) #define DEFAULT_PMBASE 0x1000 #define DEFAULT_GPIOBASE 0x1400 #define DEFAULT_GPIOSIZE 0x400 @@ -177,7 +177,7 @@ void pch_disable_devfn(struct device *dev); u32 pch_iobp_read(u32 address); void pch_iobp_write(u32 address, u32 data); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); -#if IS_ENABLED(CONFIG_ELOG) +#if CONFIG(ELOG) void pch_log_state(void); #endif void acpi_create_intel_hpet(acpi_hpet_t * hpet); diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index b14c1f7c91..3c63723f72 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -26,7 +26,7 @@ #include <console/console.h> #include "pch.h" -#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP) +#if CONFIG(INTEL_LYNXPOINT_LP) #include "lp_gpio.h" #endif diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index cf70d21ad9..426fb4233d 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -28,7 +28,7 @@ void southbridge_smm_clear_state(void) { u32 smi_en; -#if IS_ENABLED(CONFIG_ELOG) +#if CONFIG(ELOG) /* Log events from chipset before clearing */ pch_log_state(); #endif diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 8c46ab0255..bfa112a807 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -135,13 +135,13 @@ static void southbridge_smi_sleep(void) mainboard_smi_sleep(slp_typ); /* USB sleep preparations */ -#if !IS_ENABLED(CONFIG_FINALIZE_USB_ROUTE_XHCI) +#if !CONFIG(FINALIZE_USB_ROUTE_XHCI) usb_ehci_sleep_prepare(PCH_EHCI1_DEV, slp_typ); usb_ehci_sleep_prepare(PCH_EHCI2_DEV, slp_typ); #endif usb_xhci_sleep_prepare(PCH_XHCI_DEV, slp_typ); -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= ACPI_S3) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); @@ -248,7 +248,7 @@ static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) return NULL; } -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -333,7 +333,7 @@ static void southbridge_smi_apmc(void) case 0xca: usb_xhci_route_all(); break; -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) case APM_CNT_ELOG_GSMI: southbridge_smi_gsmi(); break; @@ -352,7 +352,7 @@ static void southbridge_smi_pm1(void) */ if (pm1_sts & PWRBTN_STS) { // power button pressed -#if IS_ENABLED(CONFIG_ELOG_GSMI) +#if CONFIG(ELOG_GSMI) elog_add_event(ELOG_TYPE_POWER_BUTTON); #endif disable_pm1_control(-1UL); |