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-rw-r--r--src/southbridge/intel/lynxpoint/pch.c20
-rw-r--r--src/southbridge/intel/lynxpoint/pch.h3
2 files changed, 22 insertions, 1 deletions
diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c
index 6f03716283..b4f64e1436 100644
--- a/src/southbridge/intel/lynxpoint/pch.c
+++ b/src/southbridge/intel/lynxpoint/pch.c
@@ -65,6 +65,26 @@ int pch_is_lp(void)
return pch_silicon_type() == PCH_TYPE_LPT_LP;
}
+u16 get_pmbase(void)
+{
+ static u16 pmbase;
+
+ if (!pmbase)
+ pmbase = pci_read_config16(pch_get_lpc_device(),
+ PMBASE) & 0xfffc;
+ return pmbase;
+}
+
+u16 get_gpiobase(void)
+{
+ static u16 gpiobase;
+
+ if (!gpiobase)
+ gpiobase = pci_read_config16(pch_get_lpc_device(),
+ GPIOBASE) & 0xfffc;
+ return gpiobase;
+}
+
#ifndef __SMM__
/* Set bit in Function Disble register to hide this device */
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 38202b5690..db9bb776f7 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -130,7 +130,8 @@ void pch_config_rcba(const struct rcba_config_instruction *rcba_config);
int pch_silicon_revision(void);
int pch_silicon_type(void);
int pch_is_lp(void);
-
+u16 get_pmbase(void);
+u16 get_gpiobase(void);
#if !defined(__PRE_RAM__) && !defined(__SMM__)
#include <device/device.h>
#include <arch/acpi.h>