diff options
Diffstat (limited to 'src/southbridge/intel')
44 files changed, 163 insertions, 163 deletions
diff --git a/src/southbridge/intel/esb6300/chip.h b/src/southbridge/intel/esb6300/chip.h index ff74e615fd..4082769cce 100644 --- a/src/southbridge/intel/esb6300/chip.h +++ b/src/southbridge/intel/esb6300/chip.h @@ -1,4 +1,4 @@ -struct southbridge_intel_esb6300_config +struct southbridge_intel_esb6300_config { #define ESB6300_GPIO_USE_MASK 0x03 #define ESB6300_GPIO_USE_DEFAULT 0x00 diff --git a/src/southbridge/intel/esb6300/esb6300.c b/src/southbridge/intel/esb6300/esb6300.c index 786daea23b..5d8f5e412d 100644 --- a/src/southbridge/intel/esb6300/esb6300.c +++ b/src/southbridge/intel/esb6300/esb6300.c @@ -25,7 +25,7 @@ void esb6300_enable(device_t dev) (lpc_dev->device != PCI_DEVICE_ID_INTEL_6300ESB_LPC)) { uint32_t id; id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); - if (id != (PCI_VENDOR_ID_INTEL | + if (id != (PCI_VENDOR_ID_INTEL | (PCI_DEVICE_ID_INTEL_6300ESB_LPC << 16))) { return; } @@ -39,7 +39,7 @@ void esb6300_enable(device_t dev) if (reg != reg_old) { pci_write_config16(lpc_dev, 0xf2, reg); } - + } struct chip_operations southbridge_intel_esb6300_ops = { diff --git a/src/southbridge/intel/esb6300/esb6300_ac97.c b/src/southbridge/intel/esb6300/esb6300_ac97.c index 231f8129ad..7b7795f5df 100644 --- a/src/southbridge/intel/esb6300/esb6300_ac97.c +++ b/src/southbridge/intel/esb6300/esb6300_ac97.c @@ -8,7 +8,7 @@ static void ac97_set_subsystem(device_t dev, unsigned vendor, unsigned device) { /* Write the subsystem vendor and device id */ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); } diff --git a/src/southbridge/intel/esb6300/esb6300_early_smbus.c b/src/southbridge/intel/esb6300/esb6300_early_smbus.c index ae7cfcd227..d804fde038 100644 --- a/src/southbridge/intel/esb6300/esb6300_early_smbus.c +++ b/src/southbridge/intel/esb6300/esb6300_early_smbus.c @@ -12,7 +12,7 @@ static void enable_smbus(void) pci_write_config8(dev, 0x4, 1); /* SMBALERT_DIS */ pci_write_config8(dev, 0x11, 4); - + /* Disable interrupt generation */ outb(0, SMBUS_IO_BASE + SMBHSTCTL); } @@ -30,7 +30,7 @@ static void smbus_write_byte(unsigned device, unsigned address, unsigned char va return; } -static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, +static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, unsigned data1, unsigned data2) { unsigned char global_control_register; @@ -41,11 +41,11 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, /* chear the PM timeout flags, SECOND_TO_STS */ outw(inw(0x0400 + 0x66), 0x0400 + 0x66); - + if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) { return -2; } - + /* setup transaction */ /* Obtain ownership */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); @@ -56,39 +56,39 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT); /* disable interrupts */ outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); - + /* set the device I'm talking too */ outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD); - + /* set the command address */ outb(cmd & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); - + /* set the block length */ outb(length & 0xFF, SMBUS_IO_BASE + SMBHSTDAT0); - + /* try sending out the first byte of data here */ byte=(data1>>(0))&0x0ff; outb(byte,SMBUS_IO_BASE + SMBBLKDAT); /* issue a block write command */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40, + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40, SMBUS_IO_BASE + SMBHSTCTL); for(i=0;i<length;i++) { - + /* poll for transaction completion */ if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) { return -3; } - + /* load the next byte */ if(i>3) byte=(data2>>(i%4))&0x0ff; else byte=(data1>>(i))&0x0ff; outb(byte,SMBUS_IO_BASE + SMBBLKDAT); - + /* clear the done bit */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); } diff --git a/src/southbridge/intel/esb6300/esb6300_ehci.c b/src/southbridge/intel/esb6300/esb6300_ehci.c index 8c20c0325f..c103c4bd2f 100644 --- a/src/southbridge/intel/esb6300/esb6300_ehci.c +++ b/src/southbridge/intel/esb6300/esb6300_ehci.c @@ -11,7 +11,7 @@ static void ehci_init(struct device *dev) printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); cmd = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, + pci_write_config32(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER); printk(BIOS_DEBUG, "done.\n"); @@ -24,7 +24,7 @@ static void ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device) /* Enable writes to protected registers */ pci_write_config8(dev, 0x80, access_cntl | 1); /* Write the subsystem vendor and device id */ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); /* Restore protection */ pci_write_config8(dev, 0x80, access_cntl); diff --git a/src/southbridge/intel/esb6300/esb6300_ide.c b/src/southbridge/intel/esb6300/esb6300_ide.c index 543468dabb..abe86a811d 100644 --- a/src/southbridge/intel/esb6300/esb6300_ide.c +++ b/src/southbridge/intel/esb6300/esb6300_ide.c @@ -16,7 +16,7 @@ static void ide_init(struct device *dev) pci_write_config8(dev, 0x48, 0x05); pci_write_config16(dev, 0x4a, 0x0101); pci_write_config16(dev, 0x54, 0x5055); - + #if 0 uint16_t word; word = pci_read_config16(dev, 0x40); @@ -32,7 +32,7 @@ static void ide_init(struct device *dev) static void esb6300_ide_set_subsystem(device_t dev, unsigned vendor, unsigned device) { /* This value is also visible in uchi[0-2] and smbus functions */ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); } diff --git a/src/southbridge/intel/esb6300/esb6300_lpc.c b/src/southbridge/intel/esb6300/esb6300_lpc.c index fe035bb2c4..66ac62bb3f 100644 --- a/src/southbridge/intel/esb6300/esb6300_lpc.c +++ b/src/southbridge/intel/esb6300/esb6300_lpc.c @@ -96,7 +96,7 @@ static void set_esb6300_gpio_direction( switch(config->gpio[i] & ESB6300_GPIO_SEL_MASK) { case ESB6300_GPIO_SEL_OUTPUT: val = 0; break; case ESB6300_GPIO_SEL_INPUT: val = 1; break; - default: + default: continue; } /* The caller is responsible for not playing with unimplemented bits */ @@ -133,7 +133,7 @@ static void set_esb6300_gpio_level( case ESB6300_GPIO_LVL_LOW: val = 0; blink = 0; break; case ESB6300_GPIO_LVL_HIGH: val = 1; blink = 0; break; case ESB6300_GPIO_LVL_BLINK: val = 1; blink = 1; break; - default: + default: continue; } /* The caller is responsible for not playing with unimplemented bits */ @@ -166,7 +166,7 @@ static void set_esb6300_gpio_inv( switch(config->gpio[i] & ESB6300_GPIO_INV_MASK) { case ESB6300_GPIO_INV_OFF: val = 0; break; case ESB6300_GPIO_INV_ON: val = 1; break; - default: + default: continue; } gpio_inv &= ~( 1 << i); @@ -210,7 +210,7 @@ static void esb6300_gpio_init(device_t dev) /* Find the GPIO bar */ res = find_resource(dev, GPIO_BAR); if (!res) { - return; + return; } /* Set the use selects */ @@ -274,7 +274,7 @@ static void lpc_init(struct device *dev) pci_write_config8(dev, 0xa0, 0x20); pci_write_config8(dev, 0xad, 0x03); pci_write_config8(dev, 0xbb, 0x09); - + esb6300_enable_serial_irqs(dev); esb6300_pci_dma_cfg(dev); @@ -292,7 +292,7 @@ static void lpc_init(struct device *dev) /* Set up the PIRQ */ esb6300_pirq_init(dev); - + /* Set the state of the gpio lines */ esb6300_gpio_init(dev); @@ -346,7 +346,7 @@ static void esb6300_lpc_enable_resources(device_t dev) acpi_cntl = pci_read_config8(dev, 0x44); acpi_cntl |= (1 << 4); pci_write_config8(dev, 0x44, acpi_cntl); - + /* Enable the GPIO bar */ gpio_cntl = pci_read_config8(dev, 0x5c); gpio_cntl |= (1 << 4); diff --git a/src/southbridge/intel/esb6300/esb6300_pic.c b/src/southbridge/intel/esb6300/esb6300_pic.c index 9d02536cd4..5bbf317411 100644 --- a/src/southbridge/intel/esb6300/esb6300_pic.c +++ b/src/southbridge/intel/esb6300/esb6300_pic.c @@ -40,7 +40,7 @@ static void pic_read_resources(device_t dev) res->limit = res->base + res->size -1; res->align = 8; res->gran = 8; - res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; } diff --git a/src/southbridge/intel/esb6300/esb6300_sata.c b/src/southbridge/intel/esb6300/esb6300_sata.c index 5818df1819..6dce2d2f3a 100644 --- a/src/southbridge/intel/esb6300/esb6300_sata.c +++ b/src/southbridge/intel/esb6300/esb6300_sata.c @@ -15,37 +15,37 @@ static void sata_init(struct device *dev) /* SATA configuration */ pci_write_config8(dev, 0x04, 0x07); pci_write_config8(dev, 0x09, 0x8f); - + /* Set timmings */ pci_write_config16(dev, 0x40, 0x0a307); pci_write_config16(dev, 0x42, 0x0a307); - + /* Sync DMA */ pci_write_config16(dev, 0x48, 0x000f); pci_write_config16(dev, 0x4a, 0x1111); - + /* 66 mhz */ pci_write_config16(dev, 0x54, 0xf00f); - + /* Combine ide - sata configuration */ pci_write_config8(dev, 0x90, 0x0); - + /* port 0 & 1 enable */ pci_write_config8(dev, 0x92, 0x33); - + /* initialize SATA */ pci_write_config16(dev, 0xa0, 0x0018); pci_write_config32(dev, 0xa4, 0x00000264); pci_write_config16(dev, 0xa0, 0x0040); pci_write_config32(dev, 0xa4, 0x00220043); - + printk(BIOS_DEBUG, "SATA Enabled\n"); } static void esb6300_sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) { /* This value is also visible in usb1, usb2 and smbus functions */ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); } @@ -66,7 +66,7 @@ static const struct pci_driver sata_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_6300ESB_SATA, }; - + static const struct pci_driver sata_driver_nr __pci_driver = { .ops = &sata_ops, .vendor = PCI_VENDOR_ID_INTEL, diff --git a/src/southbridge/intel/esb6300/esb6300_smbus.h b/src/southbridge/intel/esb6300/esb6300_smbus.h index 0b793c37f9..e7a0d5c711 100644 --- a/src/southbridge/intel/esb6300/esb6300_smbus.h +++ b/src/southbridge/intel/esb6300/esb6300_smbus.h @@ -10,7 +10,7 @@ #define SMBTRNSADD 0x9 #define SMBSLVDATA 0xa #define SMLINK_PIN_CTL 0xe -#define SMBUS_PIN_CTL 0xf +#define SMBUS_PIN_CTL 0xf #define SMBUS_TIMEOUT (100*1000*10) diff --git a/src/southbridge/intel/esb6300/esb6300_uhci.c b/src/southbridge/intel/esb6300/esb6300_uhci.c index 10b1dfa1cc..a8bcd888f1 100644 --- a/src/southbridge/intel/esb6300/esb6300_uhci.c +++ b/src/southbridge/intel/esb6300/esb6300_uhci.c @@ -12,7 +12,7 @@ static void uhci_init(struct device *dev) #if 1 printk(BIOS_DEBUG, "UHCI: Setting up controller.. "); cmd = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, + pci_write_config32(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER); diff --git a/src/southbridge/intel/i3100/i3100_lpc.c b/src/southbridge/intel/i3100/i3100_lpc.c index d629e2f144..eaa81e40c7 100644 --- a/src/southbridge/intel/i3100/i3100_lpc.c +++ b/src/southbridge/intel/i3100/i3100_lpc.c @@ -230,9 +230,9 @@ static void i3100_power_options(device_t dev) { /* avoid #S4 assertions */ reg8 |= (3 << 4); /* minimum asssertion is 1 to 2 RTCCLK */ - reg8 &= ~(1 << 3); + reg8 &= ~(1 << 3); pci_write_config8(dev, GEN_PMCON_3, reg8); - printk(BIOS_INFO, "set power %s after power fail\n", pwr_on ? "on" : "off"); + printk(BIOS_INFO, "set power %s after power fail\n", pwr_on ? "on" : "off"); /* Set up NMI on errors. */ reg8 = inb(0x61); @@ -245,14 +245,14 @@ static void i3100_power_options(device_t dev) { /* PCI SERR# Disable for now */ reg8 |= (1 << 2); outb(reg8, 0x61); - + reg8 = inb(0x70); nmi_option = NMI_OFF; get_option(&nmi_option, "nmi"); if (nmi_option) { /* Set NMI. */ printk(BIOS_INFO, "NMI sources enabled.\n"); - reg8 &= ~(1 << 7); + reg8 &= ~(1 << 7); } else { /* Can't mask NMI from PCI-E and NMI_NOW */ printk(BIOS_INFO, "NMI sources disabled.\n"); @@ -267,7 +267,7 @@ static void i3100_power_options(device_t dev) { /* CLKRUN_EN */ // reg16 |= (1 << 2); pci_write_config16(dev, GEN_PMCON_1, reg16); - + // Set the board's GPI routing. // i82801gx_gpi_routing(dev); } @@ -321,7 +321,7 @@ static void lpc_init(struct device *dev) // TODO this code sets int 0 of the IOAPIC in Virtual Wire Mode // (register 0x10/0x11) while the old code used int 1 (register 0x12) - // ... Why? + // ... Why? setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IOAPIC ID /* Decode 0xffc00000 - 0xffffffff to fwh idsel 0 */ diff --git a/src/southbridge/intel/i3100/i3100_sata.c b/src/southbridge/intel/i3100/i3100_sata.c index cafb68fe0d..14c13da290 100644 --- a/src/southbridge/intel/i3100/i3100_sata.c +++ b/src/southbridge/intel/i3100/i3100_sata.c @@ -73,29 +73,29 @@ static void sata_init(struct device *dev) /* IDE I/O configuration */ pci_write_config32(dev, SATA_IIOC, 0); - + } else { /* SATA configuration */ pci_write_config8(dev, SATA_CMD, 0x07); pci_write_config8(dev, SATA_PI, 0x8f); - + /* Set timings */ pci_write_config16(dev, SATA_PTIM, 0x0a307); pci_write_config16(dev, SATA_STIM, 0x0a307); - + /* Sync DMA */ pci_write_config8(dev, SATA_SYNCC, 0x0f); pci_write_config16(dev, SATA_SYNCTIM, 0x1111); - + /* Fast ATA */ pci_write_config16(dev, SATA_IIOC, 0x1000); - + /* Select IDE mode */ pci_write_config8(dev, SATA_MAP, 0x00); - + /* Enable ports 0-3 */ pci_write_config8(dev, SATA_PCS + 1, 0x0f); - + } printk(BIOS_DEBUG, "SATA Enabled\n"); } diff --git a/src/southbridge/intel/i82371eb/i82371eb_smbus.h b/src/southbridge/intel/i82371eb/i82371eb_smbus.h index a1ede98eb6..1c6f26a47d 100644 --- a/src/southbridge/intel/i82371eb/i82371eb_smbus.h +++ b/src/southbridge/intel/i82371eb/i82371eb_smbus.h @@ -31,9 +31,9 @@ static int smbus_wait_until_ready(unsigned smbus_io_base) if ((val & 0x1) == 0) { break; } -#if 0 +#if 0 if(loops == (SMBUS_TIMEOUT / 2)) { - outw(inw(smbus_io_base + SMBHST_STATUS), + outw(inw(smbus_io_base + SMBHST_STATUS), smbus_io_base + SMBHST_STATUS); } #endif @@ -48,10 +48,10 @@ static int smbus_wait_until_done(unsigned smbus_io_base) do { unsigned short val; smbus_delay(); - + val = inb(smbus_io_base + SMBHST_STATUS); // Make sure the command is done - if ((val & 0x1) != 0) { + if ((val & 0x1) != 0) { continue; } // Don't break out until one of the interrupt @@ -71,7 +71,7 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) if (smbus_wait_until_ready(smbus_io_base) < 0) { return SMBUS_WAIT_UNTIL_READY_TIMEOUT; } - + /* setup transaction */ /* disable interrupts */ outw(inw(smbus_io_base + SMBHST_CTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBHST_CTL); @@ -117,7 +117,7 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned if (smbus_wait_until_ready(smbus_io_base) < 0) { return SMBUS_WAIT_UNTIL_READY_TIMEOUT; } - + /* setup transaction */ /* disable interrupts */ outw(inw(smbus_io_base + SMBHST_CTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBHST_CTL); @@ -160,7 +160,7 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned if (smbus_wait_until_ready(smbus_io_base) < 0) { return SMBUS_WAIT_UNTIL_READY_TIMEOUT; } - + /* setup transaction */ /* clear any lingering errors, so the transaction will run */ diff --git a/src/southbridge/intel/i82801ax/i82801ax_ide.c b/src/southbridge/intel/i82801ax/i82801ax_ide.c index 2daa986bd4..da3e404d26 100644 --- a/src/southbridge/intel/i82801ax/i82801ax_ide.c +++ b/src/southbridge/intel/i82801ax/i82801ax_ide.c @@ -32,7 +32,7 @@ typedef struct southbridge_intel_i82801ax_config config_t; static void ide_init(struct device *dev) { /* Get the chip configuration */ - config_t *config = dev->chip_info; + config_t *config = dev->chip_info; /* TODO: Needs to be tested for compatibility with ICH5(R). */ /* Enable IDE devices so the Linux IDE driver will work. */ diff --git a/src/southbridge/intel/i82801ax/i82801ax_lpc.c b/src/southbridge/intel/i82801ax/i82801ax_lpc.c index 8fccdf0983..50be866be3 100644 --- a/src/southbridge/intel/i82801ax/i82801ax_lpc.c +++ b/src/southbridge/intel/i82801ax/i82801ax_lpc.c @@ -68,8 +68,8 @@ typedef struct southbridge_intel_i82801ax_config config_t; #define PIRQG 0x0A #define PIRQH 0x0B -/* - * Use 0x0ef8 for a bitmap to cover all these IRQ's. +/* + * Use 0x0ef8 for a bitmap to cover all these IRQ's. * Use the defined IRQ values above or set mainboard * specific IRQ values in your mainboards Config.lb. */ diff --git a/src/southbridge/intel/i82801bx/i82801bx_ide.c b/src/southbridge/intel/i82801bx/i82801bx_ide.c index ffbaf80dbd..9d287b2b9b 100644 --- a/src/southbridge/intel/i82801bx/i82801bx_ide.c +++ b/src/southbridge/intel/i82801bx/i82801bx_ide.c @@ -32,7 +32,7 @@ typedef struct southbridge_intel_i82801bx_config config_t; static void ide_init(struct device *dev) { /* Get the chip configuration */ - config_t *config = dev->chip_info; + config_t *config = dev->chip_info; /* TODO: Needs to be tested for compatibility with ICH5(R). */ /* Enable IDE devices so the Linux IDE driver will work. */ diff --git a/src/southbridge/intel/i82801bx/i82801bx_lpc.c b/src/southbridge/intel/i82801bx/i82801bx_lpc.c index c63de08c2a..96dbd54e37 100644 --- a/src/southbridge/intel/i82801bx/i82801bx_lpc.c +++ b/src/southbridge/intel/i82801bx/i82801bx_lpc.c @@ -68,8 +68,8 @@ typedef struct southbridge_intel_i82801bx_config config_t; #define PIRQG 0x0A #define PIRQH 0x0B -/* - * Use 0x0ef8 for a bitmap to cover all these IRQ's. +/* + * Use 0x0ef8 for a bitmap to cover all these IRQ's. * Use the defined IRQ values above or set mainboard * specific IRQ values in your mainboards Config.lb. */ diff --git a/src/southbridge/intel/i82801bx/i82801bx_smbus.h b/src/southbridge/intel/i82801bx/i82801bx_smbus.h index e4ec70bc5f..6287b631af 100644 --- a/src/southbridge/intel/i82801bx/i82801bx_smbus.h +++ b/src/southbridge/intel/i82801bx/i82801bx_smbus.h @@ -110,7 +110,7 @@ static int do_smbus_read_byte(unsigned device, unsigned address) return byte; } -/* This function is neither used nor tested by me (Corey Osgood), the author +/* This function is neither used nor tested by me (Corey Osgood), the author (Yinghai) probably tested/used it on i82801er */ static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd, unsigned data1, unsigned data2) diff --git a/src/southbridge/intel/i82801cx/chip.h b/src/southbridge/intel/i82801cx/chip.h index 99b069e82d..88415e0556 100644 --- a/src/southbridge/intel/i82801cx/chip.h +++ b/src/southbridge/intel/i82801cx/chip.h @@ -1,7 +1,7 @@ #ifndef I82801CX_CHIP_H #define I82801CX_CHIP_H -struct southbridge_intel_i82801cx_config +struct southbridge_intel_i82801cx_config { }; extern struct chip_operations southbridge_intel_i82801cx_ops; diff --git a/src/southbridge/intel/i82801cx/i82801cx.c b/src/southbridge/intel/i82801cx/i82801cx.c index ddbbc7da37..685c931fc8 100644 --- a/src/southbridge/intel/i82801cx/i82801cx.c +++ b/src/southbridge/intel/i82801cx/i82801cx.c @@ -19,7 +19,7 @@ void i82801cx_enable(device_t dev) // Calculate disable bit position for specified device:function // NOTE: For ICH-3, only the following devices can be disabled: - // D31:F1, D31:F3, D31:F5, D31:F6, + // D31:F1, D31:F3, D31:F5, D31:F6, // D29:F0, D29:F1, D29:F2 if (PCI_SLOT(dev->path.pci.devfn) == 31) { diff --git a/src/southbridge/intel/i82801cx/i82801cx.h b/src/southbridge/intel/i82801cx/i82801cx.h index ea7d858d14..e0d377a9cd 100644 --- a/src/southbridge/intel/i82801cx/i82801cx.h +++ b/src/southbridge/intel/i82801cx/i82801cx.h @@ -70,9 +70,9 @@ void i82801cx_hard_reset(void); #define SMBTRNSADD 9 #define SMBSLVDATA 10 #define SMLINK_PIN_CTL 14 -#define SMBUS_PIN_CTL 15 +#define SMBUS_PIN_CTL 15 -/* Between 1-10 seconds, We should never timeout normally +/* Between 1-10 seconds, We should never timeout normally * Longer than this is just painful when a timeout condition occurs. */ #define SMBUS_TIMEOUT (100*1000) diff --git a/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c b/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c index 02420ef75b..b62db80f9c 100644 --- a/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c +++ b/src/southbridge/intel/i82801cx/i82801cx_early_smbus.c @@ -10,9 +10,9 @@ static void enable_smbus(void) pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); /* Set smbus enable */ pci_write_config8(dev, HOSTC, HST_EN); - /* Set smbus iospace enable */ + /* Set smbus iospace enable */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - /* Disable interrupt generation */ + /* Disable interrupt generation */ outb(0, SMBUS_IO_BASE + SMBHSTCTL); /* clear any lingering errors, so the transaction will run */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); @@ -55,7 +55,7 @@ static int smbus_wait_until_ready(void) } if(loops == (SMBUS_TIMEOUT / 2)) { // Clear status flags - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); } } while(--loops); @@ -69,7 +69,7 @@ static int smbus_wait_until_done(void) do { unsigned char val; smbus_delay(); - + val = inb(SMBUS_IO_BASE + SMBHSTSTAT); // !HOST_BUSY? if ( (val & 1) == 0) { @@ -92,7 +92,7 @@ static int smbus_read_byte(unsigned device, unsigned address) if (smbus_wait_until_ready() < 0) { return -2; } - + /* setup transaction */ /* disable interrupts */ outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xfe, SMBUS_IO_BASE + SMBHSTCTL); diff --git a/src/southbridge/intel/i82801cx/i82801cx_lpc.c b/src/southbridge/intel/i82801cx/i82801cx_lpc.c index 7523b03f80..97b2994abf 100644 --- a/src/southbridge/intel/i82801cx/i82801cx_lpc.c +++ b/src/southbridge/intel/i82801cx/i82801cx_lpc.c @@ -23,7 +23,7 @@ #define MAINBOARD_POWER_ON 1 -static void i82801cx_enable_ioapic( struct device *dev) +static void i82801cx_enable_ioapic( struct device *dev) { uint32_t dword; volatile uint32_t* ioapic_index = (volatile uint32_t*)0xfec00000; @@ -36,12 +36,12 @@ static void i82801cx_enable_ioapic( struct device *dev) dword |= (1 << 2); /* DMA collection buf enable */ pci_write_config32(dev, GEN_CNTL, dword); printk(BIOS_DEBUG, "ioapic southbridge enabled %x\n",dword); - + // Must program the APIC's ID before using it *ioapic_index = 0; // Select APIC ID register *ioapic_data = (2<<24); - + // Hang if the ID didn't take (chip not present?) *ioapic_index = 0; dword = *ioapic_data; @@ -65,11 +65,11 @@ static void i82801cx_enable_serial_irqs( struct device *dev) // Parameters: dev // mask - identifies whether each channel should be used for PCI DMA // (bit = 0) or LPC DMA (bit = 1). The LSb controls channel 0. -// Channel 4 is not used (reserved). +// Channel 4 is not used (reserved). // Return Value: None // Description: Route all DMA channels to either PCI or LPC. // -static void i82801cx_lpc_route_dma( struct device *dev, uint8_t mask) +static void i82801cx_lpc_route_dma( struct device *dev, uint8_t mask) { uint16_t dmaConfig; int channelIndex; @@ -105,13 +105,13 @@ static void i82801cx_rtc_init(struct device *dev) pmcon3 |= SLEEP_AFTER_POWER_FAIL; } pci_write_config8(dev, GEN_PMCON_3, pmcon3); - printk(BIOS_INFO, "set power %s after power fail\n", + printk(BIOS_INFO, "set power %s after power fail\n", pwr_on ? "on" : "off"); // See if the Safe Mode jumper is set dword = pci_read_config32(dev, GEN_STS); rtc_failed |= dword & (1 << 2); - + rtc_init(rtc_failed); } @@ -120,28 +120,28 @@ static void i82801cx_1f0_misc(struct device *dev) { // Prevent LPC disabling, enable parity errors, and SERR# (System Error) pci_write_config16(dev, PCI_COMMAND, 0x014f); - + // Set ACPI base address to 0x1100 (I/O space) pci_write_config32(dev, PMBASE, 0x00001101); - + // Enable ACPI I/O and power management pci_write_config8(dev, ACPI_CNTL, 0x10); - + // Set GPIO base address to 0x1180 (I/O space) pci_write_config32(dev, GPIO_BASE, 0x00001181); - + // Enable GPIO pci_write_config8(dev, GPIO_CNTL, 0x10); - + // Route PIRQA to IRQ11, PIRQB to IRQ3, PIRQC to IRQ5, PIRQD to IRQ10 pci_write_config32(dev, PIRQA_ROUT, 0x0A05030B); - + // Route PIRQE to IRQ7. Leave PIRQF - PIRQH unrouted. pci_write_config8(dev, PIRQE_ROUT, 0x07); - + // Enable access to the upper 128 byte bank of CMOS RAM pci_write_config8(dev, RTC_CONF, 0x04); - + // Decode 0x3F8-0x3FF (COM1) for COMA port, // 0x2F8-0x2FF (COM2) for COMB pci_write_config8(dev, COM_DEC, 0x10); @@ -149,7 +149,7 @@ static void i82801cx_1f0_misc(struct device *dev) // LPT decode defaults to 0x378-0x37F and 0x778-0x77F // Floppy decode defaults to 0x3F0-0x3F5, 0x3F7 - // Enable COMA, COMB, LPT, floppy; + // Enable COMA, COMB, LPT, floppy; // disable microcontroller, Super I/O, sound, gameport pci_write_config16(dev, LPC_EN, 0x000F); } @@ -164,7 +164,7 @@ static void lpc_init(struct device *dev) i82801cx_enable_ioapic(dev); i82801cx_enable_serial_irqs(dev); - + /* power after power fail */ /* FIXME this doesn't work! */ /* Which state do we want to goto after g3 (power restored)? @@ -187,11 +187,11 @@ static void lpc_init(struct device *dev) byte = inb(0x70); nmi_option = NMI_OFF; get_option(&nmi_option, "nmi"); - if (nmi_option) { + if (nmi_option) { byte &= ~(1 << 7); /* set NMI */ outb(byte, 0x70); } - + /* Initialize the real time clock */ i82801cx_rtc_init(dev); diff --git a/src/southbridge/intel/i82801cx/i82801cx_smbus.c b/src/southbridge/intel/i82801cx/i82801cx_smbus.c index b69bbc1d9d..324f82f286 100644 --- a/src/southbridge/intel/i82801cx/i82801cx_smbus.c +++ b/src/southbridge/intel/i82801cx/i82801cx_smbus.c @@ -9,7 +9,7 @@ void smbus_enable(void) { /* iobase addr */ - pcibios_write_config_dword(PM_BUS, PM_DEVFN, SMB_BASE, + pcibios_write_config_dword(PM_BUS, PM_DEVFN, SMB_BASE, SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); /* smbus enable */ pcibios_write_config_byte(PM_BUS, PM_DEVFN, HOSTC, HST_EN); @@ -31,13 +31,13 @@ static void smbus_wait_until_ready(void) static void smbus_wait_until_done(void) { unsigned char byte; - + // Loop while HOST_BUSY do { byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); } while((byte &1) == 1); - + // Wait for SUCCESS or error or BYTE_DONE while( (byte & ~1) == 0) { byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); diff --git a/src/southbridge/intel/i82801cx/i82801cx_usb.c b/src/southbridge/intel/i82801cx/i82801cx_usb.c index 00b668d023..28cb3572e5 100644 --- a/src/southbridge/intel/i82801cx/i82801cx_usb.c +++ b/src/southbridge/intel/i82801cx/i82801cx_usb.c @@ -12,8 +12,8 @@ static void usb_init(struct device *dev) uint32_t cmd; printk(BIOS_DEBUG, "USB: Setting up controller.. "); cmd = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, - cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + pci_write_config32(dev, PCI_COMMAND, + cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE); diff --git a/src/southbridge/intel/i82801dx/i82801dx.c b/src/southbridge/intel/i82801dx/i82801dx.c index 282ccfd247..ac904efa29 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.c +++ b/src/southbridge/intel/i82801dx/i82801dx.c @@ -38,7 +38,7 @@ void i82801dx_enable(device_t dev) // Calculate disable bit position for specified device:function // NOTE: For ICH-4, only the following devices can be disabled: - // D31: F0, F1, F3, F5, F6, + // D31: F0, F1, F3, F5, F6, // D29: F0, F1, F2, F7 if (PCI_SLOT(dev->path.pci.devfn) == 31) { diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index 885f9de0f1..1b995b1204 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -20,11 +20,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* the problem: we have 82801dbm support in fb1, and 82801er in fb2. - * fb1 code is what we want, fb2 structure is needed however. - * so we need to get fb1 code for 82801dbm into fb2 structure. +/* the problem: we have 82801dbm support in fb1, and 82801er in fb2. + * fb1 code is what we want, fb2 structure is needed however. + * so we need to get fb1 code for 82801dbm into fb2 structure. */ -/* What I did: took the 80801er stuff from fb2, verify it against the +/* What I did: took the 80801er stuff from fb2, verify it against the * db stuff in fb1, and made sure it was right. */ @@ -132,9 +132,9 @@ extern void i82801dx_enable(device_t dev); #define SMBTRNSADD 0x9 #define SMBSLVDATA 0xa #define SMLINK_PIN_CTL 0xe -#define SMBUS_PIN_CTL 0xf +#define SMBUS_PIN_CTL 0xf -/* Between 1-10 seconds, We should never timeout normally +/* Between 1-10 seconds, We should never timeout normally * Longer than this is just painful when a timeout condition occurs. */ #define SMBUS_TIMEOUT (100*1000) diff --git a/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c b/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c index 16c6e11e72..f58cd86342 100644 --- a/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c +++ b/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c @@ -32,7 +32,7 @@ #define SMLINK_PIN_CTL 0xe #define SMBUS_PIN_CTL 0xf -/* Between 1-10 seconds, We should never timeout normally +/* Between 1-10 seconds, We should never timeout normally * Longer than this is just painful when a timeout condition occurs. */ //#define SMBUS_TIMEOUT (100*1000*10) diff --git a/src/southbridge/intel/i82801ex/chip.h b/src/southbridge/intel/i82801ex/chip.h index 34a0a97ffd..f04fc3fd29 100644 --- a/src/southbridge/intel/i82801ex/chip.h +++ b/src/southbridge/intel/i82801ex/chip.h @@ -1,7 +1,7 @@ #ifndef I82801EX_CHIP_H #define I82801EX_CHIP_H -struct southbridge_intel_i82801ex_config +struct southbridge_intel_i82801ex_config { #define ICH5R_GPIO_USE_MASK 0x03 diff --git a/src/southbridge/intel/i82801ex/i82801ex.c b/src/southbridge/intel/i82801ex/i82801ex.c index bc5f04bf44..fc4164523a 100644 --- a/src/southbridge/intel/i82801ex/i82801ex.c +++ b/src/southbridge/intel/i82801ex/i82801ex.c @@ -25,7 +25,7 @@ void i82801ex_enable(device_t dev) (lpc_dev->device != PCI_DEVICE_ID_INTEL_82801ER_LPC)) { uint32_t id; id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); - if (id != (PCI_VENDOR_ID_INTEL | + if (id != (PCI_VENDOR_ID_INTEL | (PCI_DEVICE_ID_INTEL_82801ER_LPC << 16))) { return; } @@ -39,7 +39,7 @@ void i82801ex_enable(device_t dev) if (reg != reg_old) { pci_write_config16(lpc_dev, 0xf2, reg); } - + } struct chip_operations southbridge_intel_i82801ex_ops = { diff --git a/src/southbridge/intel/i82801ex/i82801ex_ac97.c b/src/southbridge/intel/i82801ex/i82801ex_ac97.c index 65502dd8cc..08efe1534d 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_ac97.c +++ b/src/southbridge/intel/i82801ex/i82801ex_ac97.c @@ -8,7 +8,7 @@ static void ac97_set_subsystem(device_t dev, unsigned vendor, unsigned device) { /* Write the subsystem vendor and device id */ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); } diff --git a/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c b/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c index 27bd3f2324..b07c77a94f 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c +++ b/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c @@ -35,7 +35,7 @@ static void smbus_write_byte(unsigned device, unsigned address, unsigned char va if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) { return; } - + print_debug("Unimplemented smbus_write_byte() called.\n"); #if 0 @@ -60,11 +60,11 @@ static void smbus_write_byte(unsigned device, unsigned address, unsigned char va /* poll for transaction completion */ smbus_wait_until_done(SMBUS_IO_BASE); -#endif +#endif return; } -static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, +static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, unsigned data1, unsigned data2) { unsigned char byte; @@ -73,11 +73,11 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, /* chear the PM timeout flags, SECOND_TO_STS */ outw(inw(0x0400 + 0x66), 0x0400 + 0x66); - + if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) { return -2; } - + /* setup transaction */ /* Obtain ownership */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); @@ -88,39 +88,39 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT); /* disable interrupts */ outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); - + /* set the device I'm talking too */ outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD); - + /* set the command address */ outb(cmd & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); - + /* set the block length */ outb(length & 0xFF, SMBUS_IO_BASE + SMBHSTDAT0); - + /* try sending out the first byte of data here */ byte=(data1>>(0))&0x0ff; outb(byte,SMBUS_IO_BASE + SMBBLKDAT); /* issue a block write command */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40, + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40, SMBUS_IO_BASE + SMBHSTCTL); for(i=0;i<length;i++) { - + /* poll for transaction completion */ if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) { return -3; } - + /* load the next byte */ if(i>3) byte=(data2>>(i%4))&0x0ff; else byte=(data1>>(i))&0x0ff; outb(byte,SMBUS_IO_BASE + SMBBLKDAT); - + /* clear the done bit */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); } diff --git a/src/southbridge/intel/i82801ex/i82801ex_ehci.c b/src/southbridge/intel/i82801ex/i82801ex_ehci.c index 17da5d94c6..8ae921d194 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_ehci.c +++ b/src/southbridge/intel/i82801ex/i82801ex_ehci.c @@ -11,7 +11,7 @@ static void ehci_init(struct device *dev) printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); cmd = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, + pci_write_config32(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER); printk(BIOS_DEBUG, "done.\n"); @@ -24,7 +24,7 @@ static void ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device) /* Enable writes to protected registers */ pci_write_config8(dev, 0x80, access_cntl | 1); /* Write the subsystem vendor and device id */ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); /* Restore protection */ pci_write_config8(dev, 0x80, access_cntl); diff --git a/src/southbridge/intel/i82801ex/i82801ex_ide.c b/src/southbridge/intel/i82801ex/i82801ex_ide.c index cd622907ab..bbab6f1cc0 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_ide.c +++ b/src/southbridge/intel/i82801ex/i82801ex_ide.c @@ -19,7 +19,7 @@ static void ide_init(struct device *dev) static void i82801ex_ide_set_subsystem(device_t dev, unsigned vendor, unsigned device) { /* This value is also visible in uchi[0-2] and smbus functions */ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); } diff --git a/src/southbridge/intel/i82801ex/i82801ex_lpc.c b/src/southbridge/intel/i82801ex/i82801ex_lpc.c index b97af3860a..8753db17e3 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_lpc.c +++ b/src/southbridge/intel/i82801ex/i82801ex_lpc.c @@ -89,7 +89,7 @@ static void set_i82801ex_gpio_direction( switch(config->gpio[i] & ICH5R_GPIO_SEL_MASK) { case ICH5R_GPIO_SEL_OUTPUT: val = 0; break; case ICH5R_GPIO_SEL_INPUT: val = 1; break; - default: + default: continue; } /* The caller is responsible for not playing with unimplemented bits */ @@ -121,7 +121,7 @@ static void set_i82801ex_gpio_level( case ICH5R_GPIO_LVL_LOW: val = 0; blink = 0; break; case ICH5R_GPIO_LVL_HIGH: val = 1; blink = 0; break; case ICH5R_GPIO_LVL_BLINK: val = 1; blink = 1; break; - default: + default: continue; } /* The caller is responsible for not playing with unimplemented bits */ @@ -152,7 +152,7 @@ static void set_i82801ex_gpio_inv( switch(config->gpio[i] & ICH5R_GPIO_INV_MASK) { case ICH5R_GPIO_INV_OFF: val = 0; break; case ICH5R_GPIO_INV_ON: val = 1; break; - default: + default: continue; } gpio_inv &= ~( 1 << i); @@ -195,7 +195,7 @@ static void i82801ex_gpio_init(device_t dev) /* Find the GPIO bar */ res = find_resource(dev, GPIO_BAR); if (!res) { - return; + return; } /* Set the use selects */ @@ -271,7 +271,7 @@ static void lpc_init(struct device *dev) /* Set up the PIRQ */ i82801ex_pirq_init(dev); - + /* Set the state of the gpio lines */ i82801ex_gpio_init(dev); @@ -283,7 +283,7 @@ static void lpc_init(struct device *dev) /* Disable IDE (needed when sata is enabled) */ pci_write_config8(dev, 0xf2, 0x60); - + enable_hpet(dev); } @@ -330,7 +330,7 @@ static void i82801ex_lpc_enable_resources(device_t dev) acpi_cntl = pci_read_config8(dev, 0x44); acpi_cntl |= (1 << 4); pci_write_config8(dev, 0x44, acpi_cntl); - + /* Enable the GPIO bar */ gpio_cntl = pci_read_config8(dev, 0x5c); gpio_cntl |= (1 << 4); diff --git a/src/southbridge/intel/i82801ex/i82801ex_pci.c b/src/southbridge/intel/i82801ex/i82801ex_pci.c index 2394844ba4..80c6e49bc0 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_pci.c +++ b/src/southbridge/intel/i82801ex/i82801ex_pci.c @@ -21,8 +21,8 @@ static void pci_init(struct device *dev) dword |= (1<<8); /* SERR# Enable */ dword |= (1<<6); /* Parity Error Response */ pci_write_config32(dev, 0x04, dword); -#endif - +#endif + word = pci_read_config16(dev, 0x1e); word |= 0xf800; /* Clear possible errors */ pci_write_config16(dev, 0x1e, word); diff --git a/src/southbridge/intel/i82801ex/i82801ex_sata.c b/src/southbridge/intel/i82801ex/i82801ex_sata.c index a490f2a8c3..9b340e9afd 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_sata.c +++ b/src/southbridge/intel/i82801ex/i82801ex_sata.c @@ -11,7 +11,7 @@ static void sata_init(struct device *dev) /* SATA configuration */ pci_write_config8(dev, 0x04, 0x07); pci_write_config8(dev, 0x09, 0x8f); - + /* Set timmings */ pci_write_config16(dev, 0x40, 0x0a307); pci_write_config16(dev, 0x42, 0x0a307); @@ -25,10 +25,10 @@ static void sata_init(struct device *dev) /* Combine ide - sata configuration */ pci_write_config8(dev, 0x90, 0x0); - + /* port 0 & 1 enable */ pci_write_config8(dev, 0x92, 0x33); - + /* initialize SATA */ pci_write_config16(dev, 0xa0, 0x0018); pci_write_config32(dev, 0xa4, 0x00000264); diff --git a/src/southbridge/intel/i82801ex/i82801ex_smbus.h b/src/southbridge/intel/i82801ex/i82801ex_smbus.h index 27acca494f..f330c0a5de 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_smbus.h +++ b/src/southbridge/intel/i82801ex/i82801ex_smbus.h @@ -10,7 +10,7 @@ #define SMBTRNSADD 0x9 #define SMBSLVDATA 0xa #define SMLINK_PIN_CTL 0xe -#define SMBUS_PIN_CTL 0xf +#define SMBUS_PIN_CTL 0xf #define SMBUS_TIMEOUT (100*1000*10) diff --git a/src/southbridge/intel/i82801ex/i82801ex_uhci.c b/src/southbridge/intel/i82801ex/i82801ex_uhci.c index fe80079d09..56536b7273 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_uhci.c +++ b/src/southbridge/intel/i82801ex/i82801ex_uhci.c @@ -12,7 +12,7 @@ static void uhci_init(struct device *dev) #if 1 printk(BIOS_DEBUG, "UHCI: Setting up controller.. "); cmd = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, + pci_write_config32(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER); diff --git a/src/southbridge/intel/i82801gx/i82801gx_azalia.c b/src/southbridge/intel/i82801gx/i82801gx_azalia.c index a4cf14c4f9..5899ad6c0e 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_azalia.c +++ b/src/southbridge/intel/i82801gx/i82801gx_azalia.c @@ -96,7 +96,7 @@ u32 cim_verb_data_size = 0; static u32 find_verb(struct device *dev, u32 viddid, u32 ** verb) { int idx=0; - + while (idx < (cim_verb_data_size / sizeof(u32))) { u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32 if (cim_verb_data[idx] != viddid) { diff --git a/src/southbridge/intel/i82870/p64h2_ioapic.c b/src/southbridge/intel/i82870/p64h2_ioapic.c index b2523ff436..0f998dda9e 100644 --- a/src/southbridge/intel/i82870/p64h2_ioapic.c +++ b/src/southbridge/intel/i82870/p64h2_ioapic.c @@ -39,9 +39,9 @@ static void p64h2_ioapic_init(device_t dev) num_p64h2_ioapics++; // A note on IOAPIC addresses: - // 0 and 1 are used for the local APICs of the dual virtual + // 0 and 1 are used for the local APICs of the dual virtual // (hyper-threaded) CPUs of physical CPU 0 (mainboard/Config.lb). - // 6 and 7 are used for the local APICs of the dual virtual + // 6 and 7 are used for the local APICs of the dual virtual // (hyper-threaded) CPUs of physical CPU 1 (mainboard/Config.lb). // 2 is used for the IOAPIC in the 82801 Southbridge (hard-coded in i82801xx_lpc.c) @@ -63,7 +63,7 @@ static void p64h2_ioapic_init(device_t dev) pWindowRegister = (volatile uint32_t*)(memoryBase + 0x10); printk(BIOS_DEBUG, "IOAPIC %d at %02x:%02x.%01x MBAR = %p DataAddr = %p\n", - apic_id, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn), + apic_id, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn), pIndexRegister, pWindowRegister); apic_id <<= 24; // Convert ID to bitmask @@ -72,13 +72,13 @@ static void p64h2_ioapic_init(device_t dev) *pWindowRegister = (*pWindowRegister & ~(0xF<<24)) | apic_id; // Set the ID if ((*pWindowRegister & (0xF<<24)) != apic_id) - die("p64h2_ioapic_init failed"); + die("p64h2_ioapic_init failed"); *pIndexRegister = 3; // Select Boot Configuration register *pWindowRegister |= 1; // Use Processor System Bus to deliver interrupts if (!(*pWindowRegister & 1)) - die("p64h2_ioapic_init failed"); + die("p64h2_ioapic_init failed"); } static struct device_operations ioapic_ops = { diff --git a/src/southbridge/intel/i82870/p64h2_pcibridge.c b/src/southbridge/intel/i82870/p64h2_pcibridge.c index a489fe53f9..89b86f5966 100644 --- a/src/southbridge/intel/i82870/p64h2_pcibridge.c +++ b/src/southbridge/intel/i82870/p64h2_pcibridge.c @@ -35,5 +35,5 @@ static const struct pci_driver pcix_driver __pci_driver = { .ops = &pcix_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82870_1F0, -}; - +}; + diff --git a/src/southbridge/intel/pxhd/pxhd_bridge.c b/src/southbridge/intel/pxhd/pxhd_bridge.c index 0a50e5a994..683ff20013 100644 --- a/src/southbridge/intel/pxhd/pxhd_bridge.c +++ b/src/southbridge/intel/pxhd/pxhd_bridge.c @@ -56,10 +56,10 @@ static unsigned int pxhd_scan_bridge(device_t dev, unsigned int max) word &= ~(3 << 9); word |= (2 << 9); pci_write_config16(dev, 0x40, word); - + /* reset the bus to make the new frequencies effective */ pci_bus_reset(&dev->link[0]); - } + } return pcix_scan_bridge(dev, max); } static void pcix_init(device_t dev) @@ -78,7 +78,7 @@ static void pcix_init(device_t dev) byte = pci_read_config8(dev, 0x04); byte |= 0x10; pci_write_config8(dev, 0x04, byte); - + /* Set drive strength */ word = pci_read_config16(dev, 0xe0); word = 0x0404; @@ -86,7 +86,7 @@ static void pcix_init(device_t dev) word = pci_read_config16(dev, 0xe4); word = 0x0404; pci_write_config16(dev, 0xe4, word); - + /* Set impedance */ word = pci_read_config16(dev, 0xe8); word = 0x0404; @@ -96,7 +96,7 @@ static void pcix_init(device_t dev) word = pci_read_config16(dev, 0x4c); word |= 1; pci_write_config16(dev, 0x4c, word); - + /* Set split transaction limits */ word = pci_read_config16(dev, 0xa8); pci_write_config16(dev, 0xaa, word); @@ -108,12 +108,12 @@ static void pcix_init(device_t dev) dword = pci_read_config32(dev, 0x04); dword |= (1<<8); pci_write_config32(dev, 0x04, dword); - + /* system and error parity enable */ dword = pci_read_config32(dev, 0x3c); dword |= (3<<16); pci_write_config32(dev, 0x3c, dword); - + /* NMI enable */ nmi_option = NMI_OFF; get_option(&nmi_option, "nmi"); @@ -122,7 +122,7 @@ static void pcix_init(device_t dev) dword |= (1<<0); pci_write_config32(dev, 0x44, dword); } - + /* Set up CRC flood enable */ dword = pci_read_config32(dev, 0xc0); if(dword) { /* do device A only */ @@ -133,7 +133,7 @@ static void pcix_init(device_t dev) dword |= (1<<1); pci_write_config32(dev, 0xc8, dword); } - + return; #endif } @@ -175,7 +175,7 @@ static void ioapic_init(device_t dev) static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); } @@ -197,14 +197,14 @@ static const struct pci_driver ioapic_driver __pci_driver = { .ops = &ioapic_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = 0x0326, - + }; static const struct pci_driver ioapic2_driver __pci_driver = { .ops = &ioapic_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = 0x0327, - + }; struct chip_operations southbridge_intel_pxhd_ops = { |