diff options
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/ibexpeak/early_thermal.c | 9 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/thermal.c | 3 |
2 files changed, 9 insertions, 3 deletions
diff --git a/src/southbridge/intel/ibexpeak/early_thermal.c b/src/southbridge/intel/ibexpeak/early_thermal.c index 9d96a34877..d23749e513 100644 --- a/src/southbridge/intel/ibexpeak/early_thermal.c +++ b/src/southbridge/intel/ibexpeak/early_thermal.c @@ -20,12 +20,15 @@ #include <arch/io.h> #include "pch.h" +#include "cpu/intel/model_2065x/model_2065x.h" +#include <cpu/x86/msr.h> /* Early thermal init, must be done prior to giving ME its memory which is done at the end of raminit. */ void early_thermal_init(void) { device_t dev; + msr_t msr; dev = PCI_DEV(0x0, 0x1f, 0x6); @@ -38,6 +41,12 @@ void early_thermal_init(void) pci_read_config32(dev, 0x40) | 5); /* Perform init. */ + /* Configure TJmax. */ + msr = rdmsr(MSR_TEMPERATURE_TARGET); + write16(0x40000012, ((msr.lo >> 16) & 0xff) << 6); + /* Northbridge temperature slope and offset. */ + write16(0x40000016, 0x7746); + /* Enable thermal data reporting, processor, PCH and northbridge. */ write16(0x4000001a, (read16(0x4000001a) & ~0xf) | 0x10f0); /* Disable temporary BAR. */ diff --git a/src/southbridge/intel/ibexpeak/thermal.c b/src/southbridge/intel/ibexpeak/thermal.c index e01a6dbc74..fa39626bf0 100644 --- a/src/southbridge/intel/ibexpeak/thermal.c +++ b/src/southbridge/intel/ibexpeak/thermal.c @@ -37,9 +37,6 @@ static void thermal_init(struct device *dev) write32(res->base + 4, 0x3a2b); write8(res->base + 0xe, 0x40); - write32(res->base + 0x12, 0x1a40); - write16(res->base + 0x16, 0x7746); - write16(res->base + 0x1a, 0x10f0); write16(res->base + 0x56, 0xffff); write16(res->base + 0x64, 0xffff); write16(res->base + 0x66, 0xffff); |