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-rw-r--r--src/southbridge/intel/fsp_bd82x6x/chip.h2
-rw-r--r--src/southbridge/intel/fsp_bd82x6x/pch.h2
-rw-r--r--src/southbridge/intel/fsp_rangeley/soc.h2
-rw-r--r--src/southbridge/intel/i82801dx/chip.h2
4 files changed, 4 insertions, 4 deletions
diff --git a/src/southbridge/intel/fsp_bd82x6x/chip.h b/src/southbridge/intel/fsp_bd82x6x/chip.h
index 8147c513fb..9d6a9e4dbd 100644
--- a/src/southbridge/intel/fsp_bd82x6x/chip.h
+++ b/src/southbridge/intel/fsp_bd82x6x/chip.h
@@ -88,4 +88,4 @@ struct southbridge_intel_fsp_bd82x6x_config {
int c2_latency;
};
-#endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */
+#endif /* SOUTHBRIDGE_INTEL_FSP_BD82X6X_CHIP_H */
diff --git a/src/southbridge/intel/fsp_bd82x6x/pch.h b/src/southbridge/intel/fsp_bd82x6x/pch.h
index 3018455cef..045c2285af 100644
--- a/src/southbridge/intel/fsp_bd82x6x/pch.h
+++ b/src/southbridge/intel/fsp_bd82x6x/pch.h
@@ -582,4 +582,4 @@ void display_fd_settings(void);
#define SPIBAR_FDATA(n) (0x3810 + (4 * n)) /* SPI flash data */
#endif /* __ACPI__ */
-#endif /* SOUTHBRIDGE_INTEL_BD82X6X_PCH_H */
+#endif /* SOUTHBRIDGE_INTEL_FSP_BD82X6X_PCH_H */
diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h
index 90610acb6a..ba0fa4e8c5 100644
--- a/src/southbridge/intel/fsp_rangeley/soc.h
+++ b/src/southbridge/intel/fsp_rangeley/soc.h
@@ -445,4 +445,4 @@ void rangeley_sb_early_initialization(void);
#endif /* __ACPI__ */
-#endif /* SOUTHBRIDGE_INTEL_RANGELEY_PCH_H */
+#endif /* SOUTHBRIDGE_INTEL_RANGELEY_SOC_H */
diff --git a/src/southbridge/intel/i82801dx/chip.h b/src/southbridge/intel/i82801dx/chip.h
index 69a59b3d53..f77413d671 100644
--- a/src/southbridge/intel/i82801dx/chip.h
+++ b/src/southbridge/intel/i82801dx/chip.h
@@ -37,4 +37,4 @@ struct southbridge_intel_i82801dx_config {
uint8_t ide1_enable;
};
-#endif /* I82801DBM_CHIP_H */
+#endif /* I82801DX_CHIP_H */