summaryrefslogtreecommitdiff
path: root/src/southbridge/intel
diff options
context:
space:
mode:
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/lynxpoint/lpc.c2
-rw-r--r--src/southbridge/intel/lynxpoint/sata.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 4b44759139..a1e026200b 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -403,7 +403,7 @@ static void enable_hpet(struct device *const dev)
reg32 &= ~(3 << 0);
RCBA32(HPTC) = reg32;
/* Read it back to stick. It's affected by posted write syndrome. */
- reg32 = RCBA32(HPTC);
+ RCBA32(HPTC);
}
static void enable_clock_gating(struct device *dev)
diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c
index aae48e7426..75bfbde2dd 100644
--- a/src/southbridge/intel/lynxpoint/sata.c
+++ b/src/southbridge/intel/lynxpoint/sata.c
@@ -144,7 +144,7 @@ static void sata_init(struct device *dev)
/* Setup register 9Ch */
reg16 = 0; /* Disable alternate ID */
- reg16 = 1 << 5; /* BWG step 12 */
+ reg16 |= (1 << 5); /* BWG step 12 */
pci_write_config16(dev, 0x9c, reg16);
/* SATA Initialization register */