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-rw-r--r--src/southbridge/intel/bd82x6x/chip.h1
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c10
-rw-r--r--src/southbridge/intel/ibexpeak/lpc.c10
3 files changed, 8 insertions, 13 deletions
diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index 29f6881fc2..4be91522d2 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -82,7 +82,6 @@ struct southbridge_intel_bd82x6x_config {
uint8_t pcie_aspm_f6;
uint8_t pcie_aspm_f7;
- int p_cnt_throttling_supported;
int c2_latency;
int docking_supported;
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 8794602978..bd3c993912 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -768,12 +768,10 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->p_lvl3_lat = 87;
fadt->flush_size = 1024;
fadt->flush_stride = 16;
- fadt->duty_offset = 1;
- if (chip->p_cnt_throttling_supported) {
- fadt->duty_width = 3;
- } else {
- fadt->duty_width = 0;
- }
+ /* P_CNT not supported */
+ fadt->duty_offset = 0;
+ fadt->duty_width = 0;
+
fadt->day_alrm = 0xd;
fadt->mon_alrm = 0x00;
fadt->century = 0x00;
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index fa1ca92d78..c7464a05f1 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -680,12 +680,10 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->p_lvl3_lat = 87;
fadt->flush_size = 1024;
fadt->flush_stride = 16;
- fadt->duty_offset = 1;
- if (chip->p_cnt_throttling_supported) {
- fadt->duty_width = 3;
- } else {
- fadt->duty_width = 0;
- }
+ /* P_CNT not supported */
+ fadt->duty_offset = 0;
+ fadt->duty_width = 0;
+
fadt->day_alrm = 0xd;
fadt->mon_alrm = 0x00;
fadt->century = 0x32;