3 files changed, 19 insertions, 24 deletions
diff --git a/src/southbridge/intel/i82801cx/i82801cx.h b/src/southbridge/intel/i82801cx/i82801cx.h
index e0d377a9cd..da518a3660 100644
--- a/src/southbridge/intel/i82801cx/i82801cx.h
+++ b/src/southbridge/intel/i82801cx/i82801cx.h
@@ -32,9 +32,7 @@ void i82801cx_hard_reset(void);
 #define RTC_POWER_FAILED		(1<<1)
 #define SLEEP_AFTER_POWER_FAIL	(1<<0)
 
-/********************************************************************/
-/*							IDE Controller                          */
-/********************************************************************/
+/* IDE controller: */
 
 // PCI Configuration Space (D31:F1)
 #define IDE_TIM_PRI		0x40		// IDE timings, primary
@@ -44,9 +42,7 @@ void i82801cx_hard_reset(void);
 // IDE_TIM bits
 #define IDE_DECODE_ENABLE	(1<<15)
 
-/********************************************************************/
-/*								SMBus                               */
-/********************************************************************/
+/* SMBus: */
 
 // PCI Configuration Space (D31:F3)
 #define SMB_BASE	0x20
diff --git a/src/southbridge/intel/i82801cx/i82801cx_lpc.c b/src/southbridge/intel/i82801cx/i82801cx_lpc.c
index 2f2c4600a2..a1ffb8f540 100644
--- a/src/southbridge/intel/i82801cx/i82801cx_lpc.c
+++ b/src/southbridge/intel/i82801cx/i82801cx_lpc.c
@@ -61,15 +61,14 @@ static void i82801cx_enable_serial_irqs( struct device *dev)
     pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0<< 0));
 }
 
-//----------------------------------------------------------------------------------
-// Function:    	i82801cx_lpc_route_dma
-// Parameters:  	dev
-//					mask - identifies whether each channel should be used for PCI DMA
-//						   (bit = 0) or LPC DMA (bit = 1). The LSb controls channel 0.
-//						   Channel 4 is not used (reserved).
-// Return Value:	None
-// Description: 	Route all DMA channels to either PCI or LPC.
-//
+/**
+ * Route all DMA channels to either PCI or LPC.
+ *
+ * @param dev TODO
+ * @param mask Identifies whether each channel should be used for PCI DMA
+ *             (bit = 0) or LPC DMA (bit = 1). The LSb controls channel 0.
+ *             Channel 4 is not used (reserved).
+ */
 static void i82801cx_lpc_route_dma( struct device *dev, uint8_t mask)
 {
     uint16_t dmaConfig;
diff --git a/src/southbridge/intel/i82870/p64h2_ioapic.c b/src/southbridge/intel/i82870/p64h2_ioapic.c
index 0f998dda9e..8af57beed7 100644
--- a/src/southbridge/intel/i82870/p64h2_ioapic.c
+++ b/src/southbridge/intel/i82870/p64h2_ioapic.c
@@ -18,15 +18,15 @@ static void p64h2_ioapic_enable(device_t dev)
     pci_write_config16(dev, PCI_COMMAND, command);
 }
 
-//----------------------------------------------------------------------------------
-// Function:        p64h2_ioapic_init
-// Parameters:      dev - PCI bus/device/function of P64H2 IOAPIC
-//                  NOTE: There are two IOAPICs per P64H2, at D28:F0 and D30:F0
-// Return Value:    None
-// Description:     Configure one of the IOAPICs in a P64H2.
-//                  Note that a PCI bus scan will detect both IOAPICs, so this function
-//                  will be called twice for each P64H2 in the system.
-//
+/**
+ * Configure one of the IOAPICs in a P64H2.
+ *
+ * Note that a PCI bus scan will detect both IOAPICs, so this function
+ * will be called twice for each P64H2 in the system.
+ *
+ * @param dev PCI bus/device/function of P64H2 IOAPIC.
+ *            NOTE: There are two IOAPICs per P64H2, at D28:F0 and D30:F0.
+ */
 static void p64h2_ioapic_init(device_t dev)
 {
     uint32_t memoryBase;