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-rw-r--r--src/southbridge/intel/bd82x6x/early_pch.c5
-rw-r--r--src/southbridge/intel/fsp_rangeley/soc.c2
-rw-r--r--src/southbridge/intel/lynxpoint/azalia.c2
-rw-r--r--src/southbridge/intel/lynxpoint/smihandler.c4
4 files changed, 5 insertions, 8 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c
index 23942feffb..88436213a0 100644
--- a/src/southbridge/intel/bd82x6x/early_pch.c
+++ b/src/southbridge/intel/bd82x6x/early_pch.c
@@ -18,12 +18,11 @@
#include <arch/cbfs.h>
#include <ip_checksum.h>
#include <device/pci_def.h>
-#include <delay.h>
-
-#include "pch.h"
/* For DMI bar. */
#include <northbridge/intel/sandybridge/sandybridge.h>
+#include "pch.h"
+
#define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)
static void
diff --git a/src/southbridge/intel/fsp_rangeley/soc.c b/src/southbridge/intel/fsp_rangeley/soc.c
index ec5cd073ed..ec66c430a9 100644
--- a/src/southbridge/intel/fsp_rangeley/soc.c
+++ b/src/southbridge/intel/fsp_rangeley/soc.c
@@ -17,10 +17,10 @@
*/
#include <console/console.h>
-#include <delay.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
+
#include "soc.h"
static int soc_revision_id = -1;
diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c
index 2deb92976e..cb1c190b39 100644
--- a/src/southbridge/intel/lynxpoint/azalia.c
+++ b/src/southbridge/intel/lynxpoint/azalia.c
@@ -21,8 +21,8 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <device/mmio.h>
-#include <delay.h>
#include <device/azalia_device.h>
+
#include "pch.h"
#include "hda_verb.h"
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index bfa112a807..88c599f782 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -15,7 +15,6 @@
* GNU General Public License for more details.
*/
-#include <delay.h>
#include <types.h>
#include <arch/io.h>
#include <device/pci_ops.h>
@@ -29,12 +28,11 @@
#include <southbridge/intel/common/finalize.h>
#include <northbridge/intel/haswell/haswell.h>
#include <cpu/intel/haswell/haswell.h>
+
#include "me.h"
#include "pch.h"
-
#include "nvs.h"
-
static u8 smm_initialized = 0;
/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located