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-rw-r--r--src/southbridge/intel/bd82x6x/Kconfig4
-rw-r--r--src/southbridge/intel/i3100/Kconfig4
-rw-r--r--src/southbridge/intel/i82801gx/Kconfig2
-rw-r--r--src/southbridge/intel/i82801ix/Kconfig2
-rw-r--r--src/southbridge/intel/ibexpeak/Kconfig4
-rw-r--r--src/southbridge/intel/lynxpoint/Kconfig4
-rw-r--r--src/southbridge/intel/sch/Kconfig4
7 files changed, 12 insertions, 12 deletions
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index 767193ec5e..970605c5e9 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -79,9 +79,9 @@ config BUILD_WITH_FAKE_IFD
support this yet. But there is a patch pending [1].
WARNING: Never write a complete coreboot.rom to your flash ROM if it
- was built with a fake IFD. It just won't work.
+ was built with a fake IFD. It just won't work.
- [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
+ [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
config IFD_BIOS_SECTION
depends on BUILD_WITH_FAKE_IFD
diff --git a/src/southbridge/intel/i3100/Kconfig b/src/southbridge/intel/i3100/Kconfig
index 9a535d7401..9dd8a38bb1 100644
--- a/src/southbridge/intel/i3100/Kconfig
+++ b/src/southbridge/intel/i3100/Kconfig
@@ -7,8 +7,8 @@ config SOUTHBRIDGE_INTEL_I3100
if SOUTHBRIDGE_INTEL_I3100
config HPET_MIN_TICKS
- hex
- default 0x90
+ hex
+ default 0x90
endif
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig
index d8c73be468..f845d1d088 100644
--- a/src/southbridge/intel/i82801gx/Kconfig
+++ b/src/southbridge/intel/i82801gx/Kconfig
@@ -34,7 +34,7 @@ config EHCI_BAR
default 0xfef00000
config BOOTBLOCK_SOUTHBRIDGE_INIT
- string
+ string
default "southbridge/intel/i82801gx/bootblock.c"
config HPET_MIN_TICKS
diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig
index d8a32e50ca..7428d00895 100644
--- a/src/southbridge/intel/i82801ix/Kconfig
+++ b/src/southbridge/intel/i82801ix/Kconfig
@@ -40,7 +40,7 @@ config HPET_MIN_TICKS
default 0x80
config BOOTBLOCK_SOUTHBRIDGE_INIT
- string
+ string
default "southbridge/intel/i82801ix/bootblock.c"
endif
diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig
index 07a5ac2899..b47bf992fd 100644
--- a/src/southbridge/intel/ibexpeak/Kconfig
+++ b/src/southbridge/intel/ibexpeak/Kconfig
@@ -69,9 +69,9 @@ config BUILD_WITH_FAKE_IFD
support this yet. But there is a patch pending [1].
WARNING: Never write a complete coreboot.rom to your flash ROM if it
- was built with a fake IFD. It just won't work.
+ was built with a fake IFD. It just won't work.
- [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
+ [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
config IFD_BIOS_SECTION
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index 0f520112cf..4797e96afd 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -71,9 +71,9 @@ config BUILD_WITH_FAKE_IFD
support this yet. But there is a patch pending [1].
WARNING: Never write a complete coreboot.rom to your flash ROM if it
- was built with a fake IFD. It just won't work.
+ was built with a fake IFD. It just won't work.
- [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
+ [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
config IFD_BIOS_SECTION
depends on BUILD_WITH_FAKE_IFD
diff --git a/src/southbridge/intel/sch/Kconfig b/src/southbridge/intel/sch/Kconfig
index d320a53332..1c0f6f0163 100644
--- a/src/southbridge/intel/sch/Kconfig
+++ b/src/southbridge/intel/sch/Kconfig
@@ -47,8 +47,8 @@ config CMC_FILE
binary.
config HPET_MIN_TICKS
- hex
- default 0x80
+ hex
+ default 0x80
endif