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-rw-r--r--src/southbridge/intel/i82801gx/early_init.c1
-rw-r--r--src/southbridge/intel/lynxpoint/early_pch.c1
2 files changed, 0 insertions, 2 deletions
diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c
index a913873348..ef48ed857a 100644
--- a/src/southbridge/intel/i82801gx/early_init.c
+++ b/src/southbridge/intel/i82801gx/early_init.c
@@ -66,7 +66,6 @@ void i82801gx_early_init(void)
enable_smbus();
- /* Setting up Southbridge. In the northbridge code. */
printk(BIOS_DEBUG, "Setting up static southbridge registers...");
i82801gx_setup_bars();
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index 80b8939c5a..e74fdc5849 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -41,7 +41,6 @@ int pch_is_lp(void)
static void pch_enable_bars(void)
{
- /* Setting up Southbridge. In the northbridge code. */
pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1);