2 files changed, 59 insertions, 12 deletions

diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c
index a6e4f5c998..d64555e668 100644
--- a/src/southbridge/intel/lynxpoint/lp_gpio.c
+++ b/src/southbridge/intel/lynxpoint/lp_gpio.c
@@ -45,19 +45,19 @@ void setup_pch_lp_gpios(const struct pch_lp_gpio_map map[])
 	u32 irqen[3] = {0};
 	u32 reset[3] = {0};
 	u32 blink = 0;
-	int set, bit;
+	int set, bit, gpio = 0;
 
-	for (config = map; config->gpio != GPIO_LIST_END; config++) {
-		if (config->gpio > MAX_GPIO_NUMBER)
-			continue;
+	for (config = map; config->conf0 != GPIO_LIST_END; config++, gpio++) {
+		if (gpio > MAX_GPIO_NUMBER)
+			break;
 
 		/* Setup Configuration registers 1 and 2 */
-		outl(config->conf0, gpio_base + GPIO_CONFIG0(config->gpio));
-		outl(config->conf1, gpio_base + GPIO_CONFIG1(config->gpio));
+		outl(config->conf0, gpio_base + GPIO_CONFIG0(gpio));
+		outl(config->conf1, gpio_base + GPIO_CONFIG1(gpio));
 
 		/* Determine set and bit based on GPIO number */
-		set = config->gpio >> 5;
-		bit = config->gpio % 32;
+		set = gpio >> 5;
+		bit = gpio % 32;
 
 		/* Apply settings to set specific bits */
 		owner[set] |= config->owner << bit;
@@ -83,7 +83,7 @@ int get_gpio(int gpio_num)
 {
 	u16 gpio_base = get_gpio_base();
 
-	if (gpio_num < MAX_GPIO_NUMBER)
+	if (gpio_num > MAX_GPIO_NUMBER)
 		return 0;
 
 	return !!(inl(gpio_base + GPIO_CONFIG0(gpio_num)) & GPI_LEVEL);
diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h
index 9666adc6e4..48a23cb084 100644
--- a/src/southbridge/intel/lynxpoint/lp_gpio.h
+++ b/src/southbridge/intel/lynxpoint/lp_gpio.h
@@ -36,7 +36,7 @@
 #define GPIO_CONFIG1(gpio)	(0x104 + ((gpio) * 8))
 
 #define MAX_GPIO_NUMBER		94 /* zero based */
-#define GPIO_LIST_END		0xff
+#define GPIO_LIST_END		0xffffffff
 
 /* conf0 */
 
@@ -54,8 +54,10 @@
 
 #define GPI_LEVEL		(1 << 30)
 
-#define GPO_LEVEL_LOW		(0 << 31)
-#define GPO_LEVEL_HIGH		(1 << 31)
+#define GPO_LEVEL_SHIFT		31
+#define GPO_LEVEL_MASK		(1 << GPO_LEVEL_SHIFT)
+#define GPO_LEVEL_LOW		(0 << GPO_LEVEL_SHIFT)
+#define GPO_LEVEL_HIGH		(1 << GPO_LEVEL_SHIFT)
 
 /* conf1 */
 
@@ -91,6 +93,51 @@
 #define GPIO_RESET_PWROK	0
 #define GPIO_RESET_RSMRST	1
 
+#define LP_GPIO_END \
+	{ .conf0 = GPIO_LIST_END }
+
+#define LP_GPIO_NATIVE \
+	{ .conf0 = GPIO_MODE_NATIVE }
+
+#define LP_GPIO_UNUSED \
+	{ .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \
+	  .owner = GPIO_OWNER_GPIO, \
+	  .conf1 = GPIO_SENSE_DISABLE }
+
+#define LP_GPIO_ACPI_SCI \
+	{ .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \
+	  .owner = GPIO_OWNER_ACPI, \
+	  .route = GPIO_ROUTE_SCI }
+
+#define LP_GPIO_ACPI_SMI \
+	{ .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \
+	  .owner = GPIO_OWNER_ACPI, \
+	  .route = GPIO_ROUTE_SMI }
+
+#define LP_GPIO_INPUT \
+	{ .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \
+	  .owner = GPIO_OWNER_GPIO }
+
+#define LP_GPIO_IRQ_EDGE \
+	{ .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_EDGE, \
+	  .owner = GPIO_OWNER_GPIO, \
+	  .irqen = GPIO_IRQ_ENABLE }
+
+#define LP_GPIO_IRQ_LEVEL \
+	{ .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, \
+	  .owner = GPIO_OWNER_GPIO, \
+	  .irqen = GPIO_IRQ_ENABLE }
+
+#define LP_GPIO_OUT_HIGH \
+	{ .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, \
+	  .owner = GPIO_OWNER_GPIO, \
+	  .conf1 = GPIO_SENSE_DISABLE }
+
+#define LP_GPIO_OUT_LOW \
+	{ .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, \
+	  .owner = GPIO_OWNER_GPIO, \
+	  .conf1 = GPIO_SENSE_DISABLE }
+
 struct pch_lp_gpio_map {
 	u8 gpio;
 	u32 conf0;