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-rw-r--r--src/southbridge/intel/i82801gx/i82801gx.c6
-rw-r--r--src/southbridge/intel/i82801gx/sata.c97
-rw-r--r--src/southbridge/intel/i82801gx/sata.h31
3 files changed, 96 insertions, 38 deletions
diff --git a/src/southbridge/intel/i82801gx/i82801gx.c b/src/southbridge/intel/i82801gx/i82801gx.c
index e3444582e0..6d97088106 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.c
+++ b/src/southbridge/intel/i82801gx/i82801gx.c
@@ -18,6 +18,7 @@
#include <device/device.h>
#include <device/pci.h>
#include "i82801gx.h"
+#include "sata.h"
#if !CONFIG_MMCONF_SUPPORT_DEFAULT
#error ICH7 requires CONFIG_MMCONF_SUPPORT_DEFAULT
@@ -31,6 +32,11 @@ void i82801gx_enable(device_t dev)
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_SERR;
pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ if (dev->path.pci.devfn == PCI_DEVFN(31, 2)) {
+ printk(BIOS_DEBUG, "Set SATA mode early\n");
+ sata_enable(dev);
+ }
}
struct chip_operations southbridge_intel_i82801gx_ops = {
diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c
index 29f878dec3..f4eabe5f45 100644
--- a/src/southbridge/intel/i82801gx/sata.c
+++ b/src/southbridge/intel/i82801gx/sata.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2016 Damien Zammit <damien@zamaudio.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -19,14 +20,56 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include "i82801gx.h"
+#include "sata.h"
typedef struct southbridge_intel_i82801gx_config config_t;
+static u8 get_ich7_sata_ports(void)
+{
+ struct device *lpc;
+
+ lpc = dev_find_slot(0, PCI_DEVFN(31, 0));
+
+ switch (pci_read_config16(lpc, PCI_DEVICE_ID)) {
+ case 0x27b0:
+ case 0x27b8:
+ return 0xf;
+ case 0x27b9:
+ case 0x27bd:
+ return 0x5;
+ case 0x27bc:
+ return 0x3;
+ default:
+ printk(BIOS_ERR,
+ "i82801gx_sata: error: cannot determine port config\n");
+ return 0;
+ }
+}
+
+void sata_enable(struct device *dev)
+{
+ /* Get the chip configuration */
+ config_t *config = dev->chip_info;
+
+ if (config->sata_ahci) {
+ /* Set map to ahci */
+ pci_write_config8(dev, SATA_MAP,
+ (pci_read_config8(dev, SATA_MAP) & ~0xc3) | 0x40);
+ } else {
+ /* Set map to ide */
+ pci_write_config8(dev, SATA_MAP,
+ pci_read_config8(dev, SATA_MAP) & ~0xc3);
+ }
+
+ /* At this point, the new pci id will appear on the bus */
+}
+
static void sata_init(struct device *dev)
{
u32 reg32;
u16 reg16;
u32 *ahci_bar;
+ u8 ports;
/* Get the chip configuration */
config_t *config = dev->chip_info;
@@ -38,7 +81,8 @@ static void sata_init(struct device *dev)
return;
}
- /* SATA configuration */
+ /* Get ICH7 SATA port config */
+ ports = get_ich7_sata_ports();
/* Enable BARs */
pci_write_config16(dev, PCI_COMMAND, 0x0007);
@@ -70,13 +114,10 @@ static void sata_init(struct device *dev)
pci_write_config32(dev, IDE_CONFIG, reg32);
/* Combine IDE - SATA configuration */
- pci_write_config8(dev, 0x90, 0x02);
+ pci_write_config8(dev, SATA_MAP, 0x02);
/* Port 0 & 1 enable */
- pci_write_config8(dev, 0x92, 0x0f);
-
- /* SATA Initialization register */
- pci_write_config32(dev, 0x94, 0x5a000180);
+ pci_write_config8(dev, SATA_PCS, 0x0f);
} else if(config->sata_ahci) {
printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n");
/* Allow both Legacy and Native mode */
@@ -86,38 +127,18 @@ static void sata_init(struct device *dev)
/* Interrupt Pin is set by D31IP.PIP */
pci_write_config8(dev, INTR_LN, 0x0a);
- /* Set timings */
- pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
- IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
- IDE_PPE0 | IDE_IE0 | IDE_TIME0);
- pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
- IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
-
- /* Sync DMA */
- pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
- pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
-
- /* Set IDE I/O Configuration */
- reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
- pci_write_config32(dev, IDE_CONFIG, reg32);
-
- /* Set Sata Controller Mode. */
- pci_write_config8(dev, 0x90, 0x40); // 40=AHCI
-
/* In ACHI mode, bit[3:0] must always be set
* (Port status is controlled through AHCI BAR)
+ * Different settings for different controller models.
*/
- pci_write_config8(dev, 0x92, 0x0f);
+ pci_write_config8(dev, SATA_PCS, ports);
ahci_bar = (u32 *)(pci_read_config32(dev, 0x27) & ~0x3ff);
ahci_bar[3] = config->sata_ports_implemented;
-
- /* SATA Initialization register */
- pci_write_config32(dev, 0x94, 0x1a000180);
} else {
printk(BIOS_DEBUG, "SATA controller in plain mode.\n");
/* Set Sata Controller Mode. No Mapping(?) */
- pci_write_config8(dev, 0x90, 0x00);
+ pci_write_config8(dev, SATA_MAP, 0x00);
/* No AHCI: clear AHCI base */
pci_write_config32(dev, 0x24, 0x00000000);
@@ -153,12 +174,12 @@ static void sata_init(struct device *dev)
pci_write_config32(dev, IDE_CONFIG, reg32);
/* Port 0 & 1 enable XXX */
- pci_write_config8(dev, 0x92, 0x15);
-
- /* SATA Initialization register */
- pci_write_config32(dev, 0x94, 0x1a000180);
+ pci_write_config8(dev, SATA_PCS, 0x15);
}
+ /* Enable clock gating for unused ports and set initialization reg */
+ pci_write_config32(dev, SATA_IR, SIF3(ports) | SIF2 | SIF1 | SCRE);
+
/* All configurations need this SATA initialization sequence */
pci_write_config8(dev, 0xa0, 0x40);
pci_write_config8(dev, 0xa6, 0x22);
@@ -179,9 +200,9 @@ static void sata_init(struct device *dev)
pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
/* Sata Initialization Register */
- reg32 = pci_read_config32(dev, 0x94);
- reg32 |= (1 << 30); // due to some bug
- pci_write_config32(dev, 0x94, reg32);
+ reg32 = pci_read_config32(dev, SATA_IR);
+ reg32 |= SCRD; // due to some bug
+ pci_write_config32(dev, SATA_IR, reg32);
}
static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
@@ -211,11 +232,11 @@ static struct device_operations sata_ops = {
static const unsigned short sata_ids[] = {
0x27c0, /* Desktop Non-AHCI and Non-RAID Mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
+ 0x27c1, /* Desktop AHCI Mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
0x27c4, /* Mobile Non-AHCI and Non-RAID Mode: 82801GBM/GHM (ICH7-M/ICH7-M DH) */
+ 0x27c5, /* Mobile AHCI Mode: 82801GBM/GHM (ICH7-M/ICH7-M DH) */
/* NOTE: Any of the below are not properly supported yet. */
- 0x27c1, /* Desktop AHCI Mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
0x27c3, /* Desktop RAID mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
- 0x27c5, /* Mobile AHCI Mode: 82801GBM/GHM (ICH7-M/ICH7-M DH) */
0x27c6, /* ICH7M DH Raid Mode: 82801GHM (ICH7-M DH) */
0
};
diff --git a/src/southbridge/intel/i82801gx/sata.h b/src/southbridge/intel/i82801gx/sata.h
new file mode 100644
index 0000000000..9eec0dfd55
--- /dev/null
+++ b/src/southbridge/intel/i82801gx/sata.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Damien Zammit <damien@zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef I82801GX_SATA_H
+#define I82801GX_SATA_H
+
+#define SATA_MAP 0x90
+#define SATA_PCS 0x92
+#define SATA_IR 0x94
+#define SIF1 0x180
+#define SIF2 (1 << 23)
+#define SIF3(ports) ((~(ports) & 0xf) << 24)
+#define SCRE (1 << 28)
+#define SCRD (1 << 30)
+
+void sata_enable(struct device *dev);
+
+#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-30 23:38:08 +0000