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-rw-r--r--src/southbridge/intel/sch/Kconfig24
-rw-r--r--src/southbridge/intel/sch/Makefile.inc8
2 files changed, 26 insertions, 6 deletions
diff --git a/src/southbridge/intel/sch/Kconfig b/src/southbridge/intel/sch/Kconfig
index 525db06dc5..4b35306a34 100644
--- a/src/southbridge/intel/sch/Kconfig
+++ b/src/southbridge/intel/sch/Kconfig
@@ -22,11 +22,31 @@ config SOUTHBRIDGE_INTEL_SCH
select TINY_BOOTBLOCK
select HAVE_USBDEBUG
+if SOUTHBRIDGE_INTEL_SCH
+
config EHCI_BAR
hex
- default 0xfef00000 if SOUTHBRIDGE_INTEL_SCH
+ default 0xfef00000
config EHCI_DEBUG_OFFSET
hex
- default 0xa0 if SOUTHBRIDGE_INTEL_SCH
+ default 0xa0
+
+config HAVE_CMC
+ bool "Add a CMC state machine binary"
+ help
+ Select this option to add a CMC state machine binary to
+ the resulting coreboot image.
+
+ Note: Without this binary coreboot will not work
+
+config CMC_FILE
+ string "Intel CMC path and filename"
+ depends on HAVE_CMC
+ default "cmc.bin"
+ help
+ The path and filename of the file to use as CMC state machine
+ binary.
+
+endif
diff --git a/src/southbridge/intel/sch/Makefile.inc b/src/southbridge/intel/sch/Makefile.inc
index 57bcf939a5..05f45ebe34 100644
--- a/src/southbridge/intel/sch/Makefile.inc
+++ b/src/southbridge/intel/sch/Makefile.inc
@@ -36,7 +36,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
romstage-$(CONFIG_USBDEBUG) += usb_debug.c
# We don't ship that, but booting without it is bound to fail
-#cbfs-files-y += cmc.bin
-#cmc.bin-name := cmc.bin
-#cmc.bin-type := 0xaa
-#cmc.bin-position := 0xfffd0000
+cbfs-files-$(CONFIG_HAVE_CMC) += cmc.bin
+cmc.bin-name := $(CONFIG_CMC_FILE)
+cmc.bin-type := 0xaa
+cmc.bin-position := 0xfffd0000