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-rw-r--r--src/southbridge/intel/esb6300/esb6300_lpc.c4
-rw-r--r--src/southbridge/intel/esb6300/esb6300_pic.c4
-rw-r--r--src/southbridge/intel/i3100/i3100_lpc.c2
-rw-r--r--src/southbridge/intel/i82371eb/i82371eb_isa.c3
-rw-r--r--src/southbridge/intel/i82801ax/i82801ax_lpc.c7
-rw-r--r--src/southbridge/intel/i82801bx/i82801bx_lpc.c7
-rw-r--r--src/southbridge/intel/i82801cx/i82801cx_lpc.c7
-rw-r--r--src/southbridge/intel/i82801dx/i82801dx.h2
-rw-r--r--src/southbridge/intel/i82801dx/i82801dx_lpc.c3
-rw-r--r--src/southbridge/intel/i82801ex/i82801ex_lpc.c2
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx.h1
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx_lpc.c3
12 files changed, 24 insertions, 21 deletions
diff --git a/src/southbridge/intel/esb6300/esb6300_lpc.c b/src/southbridge/intel/esb6300/esb6300_lpc.c
index 9a48e05303..67bcadc961 100644
--- a/src/southbridge/intel/esb6300/esb6300_lpc.c
+++ b/src/southbridge/intel/esb6300/esb6300_lpc.c
@@ -242,7 +242,7 @@ static void lpc_init(struct device *dev)
value |= (1 << 8)|(1<<7);
value |= (6 << 0)|(1<<13)|(1<<11);
pci_write_config32(dev, 0xd0, value);
- setup_ioapic(0xfec00000, 0); // don't rename IO APIC ID
+ setup_ioapic(IO_APIC_ADDR, 0); // don't rename IO APIC ID
/* disable reset timer */
pci_write_config8(dev, 0xd4, 0x02);
@@ -330,7 +330,7 @@ static void esb6300_lpc_read_resources(device_t dev)
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
diff --git a/src/southbridge/intel/esb6300/esb6300_pic.c b/src/southbridge/intel/esb6300/esb6300_pic.c
index 5bbf317411..b9bfdf1fe3 100644
--- a/src/southbridge/intel/esb6300/esb6300_pic.c
+++ b/src/southbridge/intel/esb6300/esb6300_pic.c
@@ -23,7 +23,7 @@ static void pic_init(struct device *dev)
pci_write_config8(dev, 0x3c, 0xff);
/* Setup the ioapic */
- clear_ioapic(0xfec10000);
+ clear_ioapic(IO_APIC_ADDR + 0x10000);
}
static void pic_read_resources(device_t dev)
@@ -35,7 +35,7 @@ static void pic_read_resources(device_t dev)
/* Report the pic1 mbar resource */
res = new_resource(dev, 0x44);
- res->base = 0xfec10000;
+ res->base = IO_APIC_ADDR + 0x10000;
res->size = 256;
res->limit = res->base + res->size -1;
res->align = 8;
diff --git a/src/southbridge/intel/i3100/i3100_lpc.c b/src/southbridge/intel/i3100/i3100_lpc.c
index 75cc356179..1544ecd44f 100644
--- a/src/southbridge/intel/i3100/i3100_lpc.c
+++ b/src/southbridge/intel/i3100/i3100_lpc.c
@@ -372,7 +372,7 @@ static void i3100_lpc_read_resources(device_t dev)
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
diff --git a/src/southbridge/intel/i82371eb/i82371eb_isa.c b/src/southbridge/intel/i82371eb/i82371eb_isa.c
index 1f1aef0b93..0cc46a618c 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_isa.c
+++ b/src/southbridge/intel/i82371eb/i82371eb_isa.c
@@ -25,6 +25,7 @@
#include <device/pci_ids.h>
#include <pc80/isa-dma.h>
#include <pc80/mc146818rtc.h>
+#include <arch/ioapic.h>
#include "i82371eb.h"
static void isa_init(struct device *dev)
@@ -64,7 +65,7 @@ static void sb_read_resources(struct device *dev)
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
diff --git a/src/southbridge/intel/i82801ax/i82801ax_lpc.c b/src/southbridge/intel/i82801ax/i82801ax_lpc.c
index 2d03ae870e..46878f8dce 100644
--- a/src/southbridge/intel/i82801ax/i82801ax_lpc.c
+++ b/src/southbridge/intel/i82801ax/i82801ax_lpc.c
@@ -28,6 +28,7 @@
#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include "i82801ax.h"
#define GPIO_BASE_ADDR 0x00000500 /* GPIO Base Address Register */
@@ -72,8 +73,8 @@ typedef struct southbridge_intel_i82801ax_config config_t;
static void i82801ax_enable_apic(struct device *dev)
{
u32 reg32;
- volatile u32 *ioapic_index = (volatile u32 *)0xfec00000;
- volatile u32 *ioapic_data = (volatile u32 *)0xfec00010;
+ volatile u32 *ioapic_index = (volatile u32 *)IO_APIC_ADDR;
+ volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
/* Set ACPI base address (I/O space). */
pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
@@ -266,7 +267,7 @@ static void i82801ax_lpc_read_resources(device_t dev)
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
diff --git a/src/southbridge/intel/i82801bx/i82801bx_lpc.c b/src/southbridge/intel/i82801bx/i82801bx_lpc.c
index 9432d2e788..c379428c86 100644
--- a/src/southbridge/intel/i82801bx/i82801bx_lpc.c
+++ b/src/southbridge/intel/i82801bx/i82801bx_lpc.c
@@ -28,6 +28,7 @@
#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include "i82801bx.h"
#define NMI_OFF 0
@@ -74,8 +75,8 @@ typedef struct southbridge_intel_i82801bx_config config_t;
static void i82801bx_enable_apic(struct device *dev)
{
uint32_t reg32;
- volatile uint32_t *ioapic_index = (volatile uint32_t *)0xfec00000;
- volatile uint32_t *ioapic_data = (volatile uint32_t *)0xfec00010;
+ volatile uint32_t *ioapic_index = (volatile uint32_t *)IO_APIC_ADDR;
+ volatile uint32_t *ioapic_data = (volatile uint32_t *)(IO_APIC_ADDR + 0x10);
/* Set ACPI base address (I/O space). */
pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
@@ -284,7 +285,7 @@ static void i82801bx_lpc_read_resources(device_t dev)
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
diff --git a/src/southbridge/intel/i82801cx/i82801cx_lpc.c b/src/southbridge/intel/i82801cx/i82801cx_lpc.c
index 3720262f05..2f2c4600a2 100644
--- a/src/southbridge/intel/i82801cx/i82801cx_lpc.c
+++ b/src/southbridge/intel/i82801cx/i82801cx_lpc.c
@@ -11,6 +11,7 @@
#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include "i82801cx.h"
#define NMI_OFF 0
@@ -26,8 +27,8 @@
static void i82801cx_enable_ioapic( struct device *dev)
{
uint32_t dword;
- volatile uint32_t* ioapic_index = (volatile uint32_t*)0xfec00000;
- volatile uint32_t* ioapic_data = (volatile uint32_t*)0xfec00010;
+ volatile uint32_t* ioapic_index = (volatile uint32_t*)IO_APIC_ADDR;
+ volatile uint32_t* ioapic_data = (volatile uint32_t*)(IO_APIC_ADDR + 0x10);
dword = pci_read_config32(dev, GEN_CNTL);
dword |= (3 << 7); /* enable ioapic & disable SMBus interrupts */
@@ -224,7 +225,7 @@ static void i82801cx_lpc_read_resources(device_t dev)
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h
index cbdbc963af..a38c793eda 100644
--- a/src/southbridge/intel/i82801dx/i82801dx.h
+++ b/src/southbridge/intel/i82801dx/i82801dx.h
@@ -36,8 +36,6 @@
extern void i82801dx_enable(device_t dev);
#endif
-#define IO_APIC_ADDR 0xfec00000
-
/*
* HPET Memory Address Range. Possible values:
* 0xfed00000 for FED0_0000h - FED0_03FFh
diff --git a/src/southbridge/intel/i82801dx/i82801dx_lpc.c b/src/southbridge/intel/i82801dx/i82801dx_lpc.c
index 0bba26a82f..768e70096b 100644
--- a/src/southbridge/intel/i82801dx/i82801dx_lpc.c
+++ b/src/southbridge/intel/i82801dx/i82801dx_lpc.c
@@ -29,6 +29,7 @@
#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include "i82801dx.h"
#define NMI_OFF 0
@@ -317,7 +318,7 @@ static void i82801dx_lpc_read_resources(device_t dev)
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
diff --git a/src/southbridge/intel/i82801ex/i82801ex_lpc.c b/src/southbridge/intel/i82801ex/i82801ex_lpc.c
index df05cc85b7..998360ce07 100644
--- a/src/southbridge/intel/i82801ex/i82801ex_lpc.c
+++ b/src/southbridge/intel/i82801ex/i82801ex_lpc.c
@@ -314,7 +314,7 @@ static void i82801ex_lpc_read_resources(device_t dev)
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index 559c896901..f6a54e94d5 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -32,7 +32,6 @@
#define DEFAULT_GPIOBASE 0x0480
#define DEFAULT_PMBASE 0x0500
-#define IO_APIC_ADDR 0xfec00000
#define HPET_ADDR 0xfed00000
#define DEFAULT_RCBA 0xfed1c000
diff --git a/src/southbridge/intel/i82801gx/i82801gx_lpc.c b/src/southbridge/intel/i82801gx/i82801gx_lpc.c
index d0e076730c..f486c1ebf8 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_lpc.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_lpc.c
@@ -26,6 +26,7 @@
#include <pc80/isa-dma.h>
#include <pc80/i8259.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include "i82801gx.h"
#define NMI_OFF 0
@@ -476,7 +477,7 @@ static void i82801gx_lpc_read_resources(device_t dev)
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-20 03:35:02 +0000