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-rw-r--r--src/southbridge/intel/common/spi.c58
-rw-r--r--src/southbridge/intel/i82801gx/Kconfig1
-rw-r--r--src/southbridge/intel/i82801gx/Makefile.inc1
3 files changed, 40 insertions, 20 deletions
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index a6a9ae55f0..63f6e57bcf 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -294,6 +294,7 @@ void spi_init(void)
uint8_t bios_cntl;
device_t dev;
ich9_spi_regs *ich9_spi;
+ ich7_spi_regs *ich7_spi;
uint16_t hsfs;
#ifdef __SMM__
@@ -305,26 +306,40 @@ void spi_init(void)
pci_read_config_dword(dev, 0xf0, &rcba);
/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
rcrb = (uint8_t *)(rcba & 0xffffc000);
- ich9_spi = (ich9_spi_regs *)(rcrb + 0x3800);
- cntlr.ich9_spi = ich9_spi;
- hsfs = readw_(&ich9_spi->hsfs);
- ichspi_lock = hsfs & HSFS_FLOCKDN;
- cntlr.hsfs = hsfs;
- cntlr.opmenu = ich9_spi->opmenu;
- cntlr.menubytes = sizeof(ich9_spi->opmenu);
- cntlr.optype = &ich9_spi->optype;
- cntlr.addr = &ich9_spi->faddr;
- cntlr.data = (uint8_t *)ich9_spi->fdata;
- cntlr.databytes = sizeof(ich9_spi->fdata);
- cntlr.status = &ich9_spi->ssfs;
- cntlr.control = (uint16_t *)ich9_spi->ssfc;
- cntlr.bbar = &ich9_spi->bbar;
- cntlr.preop = &ich9_spi->preop;
-
- if (cntlr.hsfs & HSFS_FDV)
- {
- writel_ (4, &ich9_spi->fdoc);
- cntlr.flmap0 = readl_(&ich9_spi->fdod);
+ if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)) {
+ ich7_spi = (ich7_spi_regs *)(rcrb + 0x3020);
+ cntlr.opmenu = ich7_spi->opmenu;
+ cntlr.menubytes = sizeof(ich7_spi->opmenu);
+ cntlr.optype = &ich7_spi->optype;
+ cntlr.addr = &ich7_spi->spia;
+ cntlr.data = (uint8_t *)ich7_spi->spid;
+ cntlr.databytes = sizeof(ich7_spi->spid);
+ cntlr.status = (uint8_t *)&ich7_spi->spis;
+ ichspi_lock = readw_(&ich7_spi->spis) & HSFS_FLOCKDN;
+ cntlr.control = &ich7_spi->spic;
+ cntlr.bbar = &ich7_spi->bbar;
+ cntlr.preop = &ich7_spi->preop;
+ } else {
+ ich9_spi = (ich9_spi_regs *)(rcrb + 0x3800);
+ cntlr.ich9_spi = ich9_spi;
+ hsfs = readw_(&ich9_spi->hsfs);
+ ichspi_lock = hsfs & HSFS_FLOCKDN;
+ cntlr.hsfs = hsfs;
+ cntlr.opmenu = ich9_spi->opmenu;
+ cntlr.menubytes = sizeof(ich9_spi->opmenu);
+ cntlr.optype = &ich9_spi->optype;
+ cntlr.addr = &ich9_spi->faddr;
+ cntlr.data = (uint8_t *)ich9_spi->fdata;
+ cntlr.databytes = sizeof(ich9_spi->fdata);
+ cntlr.status = &ich9_spi->ssfs;
+ cntlr.control = (uint16_t *)ich9_spi->ssfc;
+ cntlr.bbar = &ich9_spi->bbar;
+ cntlr.preop = &ich9_spi->preop;
+
+ if (cntlr.hsfs & HSFS_FDV) {
+ writel_ (4, &ich9_spi->fdoc);
+ cntlr.flmap0 = readl_(&ich9_spi->fdod);
+ }
}
ich_set_bbar(0);
@@ -897,6 +912,9 @@ static int spi_flash_programmer_probe(const struct spi_slave *spi,
{
uint32_t flcomp;
+ if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX))
+ return spi_flash_generic_probe(spi, flash);
+
/* Try generic probing first if spi_is_multichip returns 0. */
if (!spi_is_multichip() && !spi_flash_generic_probe(spi, flash))
return 0;
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig
index 68c236299e..fd7579ac31 100644
--- a/src/southbridge/intel/i82801gx/Kconfig
+++ b/src/southbridge/intel/i82801gx/Kconfig
@@ -23,6 +23,7 @@ config SOUTHBRIDGE_INTEL_I82801GX
select USE_WATCHDOG_ON_BOOT
select HAVE_SMI_HANDLER
select COMMON_FADT
+ select SPI_FLASH
select SOUTHBRIDGE_INTEL_COMMON_GPIO
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc
index bb68d933b6..5b3ba6ae0a 100644
--- a/src/southbridge/intel/i82801gx/Makefile.inc
+++ b/src/southbridge/intel/i82801gx/Makefile.inc
@@ -27,6 +27,7 @@ ramstage-y += sata.c
ramstage-y += smbus.c
ramstage-y += usb.c
ramstage-y += usb_ehci.c
+ramstage-y += ../common/spi.c
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c