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-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c8
-rw-r--r--src/southbridge/intel/bd82x6x/me.c10
-rw-r--r--src/southbridge/intel/bd82x6x/me_8.x.c12
-rw-r--r--src/southbridge/intel/bd82x6x/pch.h4
-rw-r--r--src/southbridge/intel/bd82x6x/usb_ehci.c4
-rw-r--r--src/southbridge/intel/common/finalize.c10
-rw-r--r--src/southbridge/intel/common/pmutil.h8
-rw-r--r--src/southbridge/intel/common/rtc.c2
-rw-r--r--src/southbridge/intel/common/smbus.c6
-rw-r--r--src/southbridge/intel/common/smi.c4
-rw-r--r--src/southbridge/intel/common/smihandler.c10
-rw-r--r--src/southbridge/intel/common/spi.c12
-rw-r--r--src/southbridge/intel/common/usb_debug.c2
-rw-r--r--src/southbridge/intel/fsp_rangeley/acpi.c2
-rw-r--r--src/southbridge/intel/fsp_rangeley/lpc.c4
-rw-r--r--src/southbridge/intel/fsp_rangeley/romstage.c2
-rw-r--r--src/southbridge/intel/fsp_rangeley/soc.h2
-rw-r--r--src/southbridge/intel/fsp_rangeley/spi.c2
-rw-r--r--src/southbridge/intel/i82371eb/isa.c12
-rw-r--r--src/southbridge/intel/i82801gx/lpc.c6
-rw-r--r--src/southbridge/intel/i82801ix/acpi/sleepstates.asl2
-rw-r--r--src/southbridge/intel/i82801ix/i82801ix.c2
-rw-r--r--src/southbridge/intel/i82801ix/i82801ix.h2
-rw-r--r--src/southbridge/intel/i82801ix/lpc.c6
-rw-r--r--src/southbridge/intel/i82801jx/acpi/sleepstates.asl2
-rw-r--r--src/southbridge/intel/i82801jx/i82801jx.c2
-rw-r--r--src/southbridge/intel/i82801jx/lpc.c4
-rw-r--r--src/southbridge/intel/ibexpeak/lpc.c8
-rw-r--r--src/southbridge/intel/ibexpeak/me.c8
-rw-r--r--src/southbridge/intel/ibexpeak/pch.h2
-rw-r--r--src/southbridge/intel/ibexpeak/smi.c2
-rw-r--r--src/southbridge/intel/ibexpeak/smihandler.c8
-rw-r--r--src/southbridge/intel/lynxpoint/acpi/pch.asl2
-rw-r--r--src/southbridge/intel/lynxpoint/early_pch.c6
-rw-r--r--src/southbridge/intel/lynxpoint/lpc.c8
-rw-r--r--src/southbridge/intel/lynxpoint/me_9.x.c22
-rw-r--r--src/southbridge/intel/lynxpoint/pch.h4
-rw-r--r--src/southbridge/intel/lynxpoint/pmutil.c2
-rw-r--r--src/southbridge/intel/lynxpoint/smi.c2
-rw-r--r--src/southbridge/intel/lynxpoint/smihandler.c10
40 files changed, 113 insertions, 113 deletions
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index de6b78c9cb..f22be9ed12 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -79,7 +79,7 @@ static void pch_enable_serial_irqs(struct device *dev)
/* Set packet length and toggle silent mode bit for one frame. */
pci_write_config8(dev, SERIRQ_CNTL,
(1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
-#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)
+#if !CONFIG(SERIRQ_CONTINUOUS_MODE)
pci_write_config8(dev, SERIRQ_CNTL,
(1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
#endif
@@ -724,7 +724,7 @@ static void southbridge_inject_dsdt(struct device *dev)
memcpy(gnvs->did, gfx->did, sizeof(gnvs->did));
}
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
chromeos_init_chromeos_acpi(&(gnvs->chromeos));
#endif
@@ -915,8 +915,8 @@ static void lpc_final(struct device *dev)
RCBA32(0x389c) = spi_opmenu[1];
/* Call SMM finalize() handlers before resume */
- if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
- if (IS_ENABLED(CONFIG_INTEL_CHIPSET_LOCKDOWN) ||
+ if (CONFIG(HAVE_SMI_HANDLER)) {
+ if (CONFIG(INTEL_CHIPSET_LOCKDOWN) ||
acpi_is_wakeup_s3()) {
outb(APM_CNT_FINALIZE, APM_CNT);
}
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 58c24784db..5731b9bcd0 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -41,7 +41,7 @@
#include "me.h"
#include "pch.h"
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
#include <vendorcode/google/chromeos/gnvs.h>
#endif
@@ -60,7 +60,7 @@ static const char *me_bios_path_values[] = {
/* MMIO base address for MEI interface */
static u32 *mei_base_address;
-#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
+#if CONFIG(DEBUG_INTEL_ME)
static void mei_dump(void *ptr, int dword, int offset, const char *type)
{
struct mei_csr *csr;
@@ -456,7 +456,7 @@ static int mkhi_get_fwcaps(void)
}
#endif
-#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */
+#if CONFIG(CHROMEOS) && 0 /* DISABLED */
/* Tell ME to issue a global reset */
int mkhi_global_reset(void)
{
@@ -588,7 +588,7 @@ static me_bios_path intel_me_path(struct device *dev)
if (hfs.error_code || hfs.fpt_bad)
path = ME_ERROR_BIOS_PATH;
-#if IS_ENABLED(CONFIG_ELOG)
+#if CONFIG(ELOG)
if (path != ME_NORMAL_BIOS_PATH) {
struct elog_event_data_me_extended data = {
.current_working_state = hfs.working_state,
@@ -677,7 +677,7 @@ static int intel_me_extend_valid(struct device *dev)
}
printk(BIOS_DEBUG, "\n");
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
/* Save hash in NVS for the OS to verify */
chromeos_set_me_hash(extend, count);
#endif
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index bdd57cdd33..a6ffe896c4 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -41,7 +41,7 @@
#include "me.h"
#include "pch.h"
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
#include <vendorcode/google/chromeos/chromeos.h>
#include <vendorcode/google/chromeos/gnvs.h>
#endif
@@ -62,7 +62,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data);
/* MMIO base address for MEI interface */
static u32 *mei_base_address;
-#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
+#if CONFIG(DEBUG_INTEL_ME)
static void mei_dump(void *ptr, int dword, int offset, const char *type)
{
struct mei_csr *csr;
@@ -423,7 +423,7 @@ static void me_print_fwcaps(mbp_fw_caps *caps_section)
}
#endif
-#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */
+#if CONFIG(CHROMEOS) && 0 /* DISABLED */
/* Tell ME to issue a global reset */
static int mkhi_global_reset(void)
{
@@ -575,7 +575,7 @@ static me_bios_path intel_me_path(struct device *dev)
path = ME_ERROR_BIOS_PATH;
}
-#if IS_ENABLED(CONFIG_ELOG)
+#if CONFIG(ELOG)
if (path != ME_NORMAL_BIOS_PATH) {
struct elog_event_data_me_extended data = {
.current_working_state = hfs.working_state,
@@ -664,7 +664,7 @@ static int intel_me_extend_valid(struct device *dev)
}
printk(BIOS_DEBUG, "\n");
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
/* Save hash in NVS for the OS to verify */
chromeos_set_me_hash(extend, count);
#endif
@@ -705,7 +705,7 @@ static void intel_me_init(struct device *dev)
if (intel_me_read_mbp(&mbp_data))
break;
-#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */
+#if CONFIG(CHROMEOS) && 0 /* DISABLED */
/*
* Unlock ME in recovery mode.
*/
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 5dac57eaf0..67b0d11415 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -47,9 +47,9 @@
#include <southbridge/intel/common/rcba.h>
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X)
+#if CONFIG(SOUTHBRIDGE_INTEL_BD82X6X)
#define CROS_GPIO_DEVICE_NAME "CougarPoint"
-#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_C216)
+#elif CONFIG(SOUTHBRIDGE_INTEL_C216)
#define CROS_GPIO_DEVICE_NAME "PantherPoint"
#endif
diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c
index e98b8bef7a..6cf4c1061b 100644
--- a/src/southbridge/intel/bd82x6x/usb_ehci.c
+++ b/src/southbridge/intel/bd82x6x/usb_ehci.c
@@ -35,7 +35,7 @@ static void usb_ehci_init(struct device *dev)
printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
/* For others, done in MRC. */
-#if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT)
+#if CONFIG(USE_NATIVE_RAMINIT)
pci_write_config32(dev, 0x84, 0x930c8811);
pci_write_config32(dev, 0x88, 0x24000d30);
pci_write_config32(dev, 0xf4, 0x80408588);
@@ -50,7 +50,7 @@ static void usb_ehci_init(struct device *dev)
pci_write_config32(dev, PCI_COMMAND, reg32);
/* For others, done in MRC. */
-#if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT)
+#if CONFIG(USE_NATIVE_RAMINIT)
struct resource *res;
u8 access_cntl;
diff --git a/src/southbridge/intel/common/finalize.c b/src/southbridge/intel/common/finalize.c
index f1c33b9b06..80c65bb028 100644
--- a/src/southbridge/intel/common/finalize.c
+++ b/src/southbridge/intel/common/finalize.c
@@ -28,11 +28,11 @@ void intel_pch_finalize_smm(void)
{
const pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0);
- if (IS_ENABLED(CONFIG_LOCK_SPI_FLASH_RO) ||
- IS_ENABLED(CONFIG_LOCK_SPI_FLASH_NO_ACCESS)) {
+ if (CONFIG(LOCK_SPI_FLASH_RO) ||
+ CONFIG(LOCK_SPI_FLASH_NO_ACCESS)) {
int i;
u32 lockmask = 1UL << 31;
- if (IS_ENABLED(CONFIG_LOCK_SPI_FLASH_NO_ACCESS))
+ if (CONFIG(LOCK_SPI_FLASH_NO_ACCESS))
lockmask |= 1 << 15;
for (i = 0; i < 20; i += 4)
RCBA32(0x3874 + i) = RCBA32(0x3854 + i) | lockmask;
@@ -41,7 +41,7 @@ void intel_pch_finalize_smm(void)
/* Lock SPIBAR */
RCBA32_OR(0x3804, (1 << 15));
- if (IS_ENABLED(CONFIG_SPI_FLASH_SMM))
+ if (CONFIG(SPI_FLASH_SMM))
/* Re-init SPI driver to handle locked BAR */
spi_init();
@@ -61,7 +61,7 @@ void intel_pch_finalize_smm(void)
pci_update_config32(lpc_dev, D31F0_ETR3, ~ETR3_CF9GR, ETR3_CF9LOCK);
- if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT))
+ if (CONFIG(SOUTHBRIDGE_INTEL_LYNXPOINT))
/* PMSYNC */
RCBA32_OR(0x33c4, (1UL << 31));
diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h
index 7f07a724a3..eb74aa57ce 100644
--- a/src/southbridge/intel/common/pmutil.h
+++ b/src/southbridge/intel/common/pmutil.h
@@ -69,13 +69,13 @@
#define LV2 0x14
#define LV3 0x15
#define LV4 0x16
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)
+#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX)
#define PM2_CNT 0x20 // mobile only
#define GPE0_STS 0x28
#else
#define PM2_CNT 0x50 // mobile only
#define GPE0_STS 0x20
-#endif /* IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) */
+#endif /* CONFIG(SOUTHBRIDGE_INTEL_I82801GX) */
#define USB4_STS (1 << 14) /* i82801gx only */
#define PME_B0_STS (1 << 13)
#define PME_STS (1 << 11)
@@ -86,11 +86,11 @@
#define TCOSCI_STS (1 << 6)
#define SWGPE_STS (1 << 2)
#define HOT_PLUG_STS (1 << 1)
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)
+#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX)
#define GPE0_EN 0x2c
#else
#define GPE0_EN 0x28
-#endif /* IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) */
+#endif /* CONFIG(SOUTHBRIDGE_INTEL_I82801GX) */
#define PME_B0_EN (1 << 13)
#define PME_EN (1 << 11)
#define TCOSCI_EN (1 << 6)
diff --git a/src/southbridge/intel/common/rtc.c b/src/southbridge/intel/common/rtc.c
index 1f0abeb450..3ee12aa169 100644
--- a/src/southbridge/intel/common/rtc.c
+++ b/src/southbridge/intel/common/rtc.c
@@ -41,7 +41,7 @@ void sb_rtc_init(void)
int rtc_failed = rtc_failure();
if (rtc_failed) {
- if (IS_ENABLED(CONFIG_ELOG))
+ if (CONFIG(ELOG))
elog_add_event(ELOG_TYPE_RTC_RESET);
pci_update_config8(PCH_LPC_DEV, D31F0_GEN_PMCON_3,
~RTC_BATTERY_DEAD, 0);
diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c
index 9ae01ad178..4b08c48f27 100644
--- a/src/southbridge/intel/common/smbus.c
+++ b/src/southbridge/intel/common/smbus.c
@@ -22,7 +22,7 @@
#include "smbus.h"
-#if IS_ENABLED(CONFIG_DEBUG_SMBUS)
+#if CONFIG(DEBUG_SMBUS)
#define dprintk(args...) printk(BIOS_DEBUG, ##args)
#else
#define dprintk(args...) do {} while (0)
@@ -369,8 +369,8 @@ int do_smbus_block_write(unsigned int smbus_base, u8 device, u8 cmd,
/* Only since ICH5 */
static int has_i2c_read_command(void)
{
- if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) ||
- IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801DX))
+ if (CONFIG(SOUTHBRIDGE_INTEL_I82371EB) ||
+ CONFIG(SOUTHBRIDGE_INTEL_I82801DX))
return 0;
return 1;
}
diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c
index 40f5412a91..036ac22adc 100644
--- a/src/southbridge/intel/common/smi.c
+++ b/src/southbridge/intel/common/smi.c
@@ -40,7 +40,7 @@ void southbridge_smm_init(void)
u16 pm1_en;
u32 gpe0_en;
- if (IS_ENABLED(CONFIG_ELOG))
+ if (CONFIG(ELOG))
/* Log events from chipset before clearing */
pch_log_state();
@@ -159,7 +159,7 @@ void southbridge_smm_clear_state(void)
{
u32 smi_en;
- if (IS_ENABLED(CONFIG_ELOG))
+ if (CONFIG(ELOG))
/* Log events from chipset before clearing */
pch_log_state();
diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c
index 05b73f20c3..b2cf49a45e 100644
--- a/src/southbridge/intel/common/smihandler.c
+++ b/src/southbridge/intel/common/smihandler.c
@@ -136,7 +136,7 @@ static void southbridge_smi_sleep(void)
/* Do any mainboard sleep handling */
mainboard_smi_sleep(slp_typ);
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
/* Log S3, S4, and S5 entry */
if (slp_typ >= ACPI_S3)
elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
@@ -244,7 +244,7 @@ em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd)
return NULL;
}
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
static void southbridge_smi_gsmi(void)
{
u32 *ret, *param;
@@ -316,7 +316,7 @@ static void southbridge_smi_apmc(void)
southbridge_finalize_all();
mainboard_finalized = 1;
break;
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
case APM_CNT_ELOG_GSMI:
southbridge_smi_gsmi();
break;
@@ -340,7 +340,7 @@ static void southbridge_smi_pm1(void)
// power button pressed
u32 reg32;
reg32 = (7 << 10) | (1 << 13);
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
elog_add_event(ELOG_TYPE_POWER_BUTTON);
#endif
write_pmbase32(PM1_CNT, reg32);
@@ -478,7 +478,7 @@ static smi_handler_t southbridge_smi[32] = {
* @param node
* @param state_save
*/
-#if IS_ENABLED(CONFIG_SMM_TSEG)
+#if CONFIG(SMM_TSEG)
void southbridge_smi_handler(void)
#else
void cpu_smi_handler(unsigned int node, smm_state_save_area_t *state_save)
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index a030ff4ef5..bf2a44c86c 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -161,7 +161,7 @@ enum {
SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3
};
-#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)
+#if CONFIG(DEBUG_SPI_FLASH)
static u8 readb_(const void *addr)
{
@@ -283,7 +283,7 @@ void spi_init(void)
rcba = pci_read_config32(dev, 0xf0);
/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
rcrb = (uint8_t *)(rcba & 0xffffc000);
- if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)) {
+ if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) {
ich7_spi = (ich7_spi_regs *)(rcrb + 0x3020);
cntlr->opmenu = ich7_spi->opmenu;
cntlr->menubytes = sizeof(ich7_spi->opmenu);
@@ -906,7 +906,7 @@ static int spi_flash_programmer_probe(const struct spi_slave *spi,
{
ich_spi_controller *cntlr = &g_cntlr;
- if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX))
+ if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX))
return spi_flash_generic_probe(spi, flash);
/* Try generic probing first if spi_is_multichip returns 0. */
@@ -963,7 +963,7 @@ static u32 spi_fpr(u32 base, u32 limit)
u32 ret;
u32 mask, limit_shift;
- if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)) {
+ if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) {
mask = ICH7_SPI_FPR_MASK;
limit_shift = ICH7_SPI_FPR_LIMIT_SHIFT;
} else {
@@ -1011,12 +1011,12 @@ static int spi_flash_protect(const struct spi_flash *flash,
protect_mask |= SPI_FPR_WPE;
break;
case READ_PROTECT:
- if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX))
+ if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX))
return -1;
protect_mask |= ICH9_SPI_FPR_RPE;
break;
case READ_WRITE_PROTECT:
- if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX))
+ if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX))
return -1;
protect_mask |= (ICH9_SPI_FPR_RPE | SPI_FPR_WPE);
break;
diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c
index 4c5fe96b0d..d60264a15b 100644
--- a/src/southbridge/intel/common/usb_debug.c
+++ b/src/southbridge/intel/common/usb_debug.c
@@ -26,7 +26,7 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
u32 class;
pci_devfn_t dev;
- if (!IS_ENABLED(CONFIG_HAVE_USBDEBUG_OPTIONS))
+ if (!CONFIG(HAVE_USBDEBUG_OPTIONS))
return PCI_DEV(0, 0x1d, 7);
if (hcd_idx == 2)
diff --git a/src/southbridge/intel/fsp_rangeley/acpi.c b/src/southbridge/intel/fsp_rangeley/acpi.c
index e111881581..e0b3cb985c 100644
--- a/src/southbridge/intel/fsp_rangeley/acpi.c
+++ b/src/southbridge/intel/fsp_rangeley/acpi.c
@@ -23,7 +23,7 @@
#include <device/pci_ops.h>
#include <version.h>
-#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+#if CONFIG(HAVE_SMI_HANDLER)
#include <cpu/x86/smm.h>
#endif
diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c
index b93bc09a62..711778e125 100644
--- a/src/southbridge/intel/fsp_rangeley/lpc.c
+++ b/src/southbridge/intel/fsp_rangeley/lpc.c
@@ -95,7 +95,7 @@ static void soc_enable_serial_irqs(struct device *dev)
/* Set packet length and toggle silent mode bit for one frame. */
write8(ibase + ILB_SERIRQ_CNTL, (1 << 7));
-#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)
+#if !CONFIG(SERIRQ_CONTINUOUS_MODE)
write8(ibase + ILB_SERIRQ_CNTL, 0);
#endif
}
@@ -435,7 +435,7 @@ static void southbridge_inject_dsdt(struct device *dev)
if (gnvs) {
memset(gnvs, 0, sizeof(*gnvs));
acpi_create_gnvs(gnvs);
-#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+#if CONFIG(HAVE_SMI_HANDLER)
/* And tell SMI about it */
smm_setup_structures(gnvs, NULL, NULL);
#endif
diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c
index 65001cfff1..2891ca4ae7 100644
--- a/src/southbridge/intel/fsp_rangeley/romstage.c
+++ b/src/southbridge/intel/fsp_rangeley/romstage.c
@@ -102,7 +102,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
__func__, (u32) status, (u32) hob_list_ptr);
/* FSP reconfigures USB, so reinit it to have debug */
- if (IS_ENABLED(CONFIG_USBDEBUG_IN_PRE_RAM))
+ if (CONFIG(USBDEBUG_IN_PRE_RAM))
usbdebug_hw_init(true);
printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status);
diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h
index 29ed943d3d..4c5e835c7f 100644
--- a/src/southbridge/intel/fsp_rangeley/soc.h
+++ b/src/southbridge/intel/fsp_rangeley/soc.h
@@ -61,7 +61,7 @@ void soc_enable(struct device *dev);
void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt);
-#if IS_ENABLED(CONFIG_ELOG)
+#if CONFIG(ELOG)
void soc_log_state(void);
#endif
#else
diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c
index 99400fcbeb..e65576769c 100644
--- a/src/southbridge/intel/fsp_rangeley/spi.c
+++ b/src/southbridge/intel/fsp_rangeley/spi.c
@@ -193,7 +193,7 @@ enum {
SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3,
};
-#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)
+#if CONFIG(DEBUG_SPI_FLASH)
static u8 readb_(const void *addr)
{
diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c
index b4041ef9e0..00b3866665 100644
--- a/src/southbridge/intel/i82371eb/isa.c
+++ b/src/southbridge/intel/i82371eb/isa.c
@@ -23,13 +23,13 @@
#include <pc80/isa-dma.h>
#include <pc80/mc146818rtc.h>
#include <arch/ioapic.h>
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
#include <arch/acpi.h>
#include <arch/acpigen.h>
#endif
#include "i82371eb.h"
-#if IS_ENABLED(CONFIG_IOAPIC)
+#if CONFIG(IOAPIC)
static void enable_intel_82093aa_ioapic(void)
{
u16 reg16;
@@ -85,7 +85,7 @@ static void isa_init(struct device *dev)
/* Initialize ISA DMA. */
isa_dma_init();
-#if IS_ENABLED(CONFIG_IOAPIC)
+#if CONFIG(IOAPIC)
/*
* Unlike most other southbridges the 82371EB doesn't have a built-in
* IOAPIC. Instead, 82371EB-based boards that support multiple CPUs
@@ -116,7 +116,7 @@ static void sb_read_resources(struct device *dev)
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED |
IORESOURCE_RESERVE;
-#if IS_ENABLED(CONFIG_IOAPIC)
+#if CONFIG(IOAPIC)
res = new_resource(dev, 3); /* IOAPIC */
res->base = IO_APIC_ADDR;
res->size = 0x00001000;
@@ -125,7 +125,7 @@ static void sb_read_resources(struct device *dev)
#endif
}
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
static void southbridge_acpi_fill_ssdt_generator(struct device *device)
{
acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS");
@@ -137,7 +137,7 @@ static const struct device_operations isa_ops = {
.read_resources = sb_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
.write_acpi_tables = acpi_write_hpet,
.acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator,
#endif
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index a08bbf8d2c..669648ba55 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -330,7 +330,7 @@ static void enable_clock_gating(void)
RCBA32(CG) = reg32;
}
-#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+#if CONFIG(HAVE_SMI_HANDLER)
static void i82801gx_lock_smm(struct device *dev)
{
#if TEST_SMM_FLASH_LOCKDOWN
@@ -445,7 +445,7 @@ static void lpc_init(struct device *dev)
/* Interrupt 9 should be level triggered (SCI) */
i8259_configure_irq_trigger(9, 1);
-#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+#if CONFIG(HAVE_SMI_HANDLER)
i82801gx_lock_smm(dev);
#endif
@@ -649,7 +649,7 @@ static void lpc_final(struct device *dev)
{
u16 tco1_cnt;
- if (!IS_ENABLED(CONFIG_INTEL_CHIPSET_LOCKDOWN))
+ if (!CONFIG(INTEL_CHIPSET_LOCKDOWN))
return;
SPIBAR16(PREOP) = SPI_OPPREFIX;
diff --git a/src/southbridge/intel/i82801ix/acpi/sleepstates.asl b/src/southbridge/intel/i82801ix/acpi/sleepstates.asl
index d7fb2a56bb..79818a109a 100644
--- a/src/southbridge/intel/i82801ix/acpi/sleepstates.asl
+++ b/src/southbridge/intel/i82801ix/acpi/sleepstates.asl
@@ -15,7 +15,7 @@
*/
Name(\_S0, Package(){0x0,0x0,0x0,0x0})
-#if !IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+#if !CONFIG(HAVE_ACPI_RESUME)
Name(\_S1, Package(){0x1,0x0,0x0,0x0})
#else
Name(\_S3, Package(){0x5,0x0,0x0,0x0})
diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c
index 991ae82259..99078dc402 100644
--- a/src/southbridge/intel/i82801ix/i82801ix.c
+++ b/src/southbridge/intel/i82801ix/i82801ix.c
@@ -224,7 +224,7 @@ static void i82801ix_init(void *chip_info)
i82801ix_hide_functions();
/* Reset watchdog timer. */
-#if !IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+#if !CONFIG(HAVE_SMI_HANDLER)
outw(0x0008, DEFAULT_TCOBASE + 0x12); /* Set higher timer value. */
#endif
outw(0x0000, DEFAULT_TCOBASE + 0x00); /* Update timer. */
diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h
index bfa875b74d..421a101bdc 100644
--- a/src/southbridge/intel/i82801ix/i82801ix.h
+++ b/src/southbridge/intel/i82801ix/i82801ix.h
@@ -28,7 +28,7 @@
#include <southbridge/intel/common/rcba.h>
-#if IS_ENABLED(CONFIG_BOARD_EMULATION_QEMU_X86_Q35)
+#if CONFIG(BOARD_EMULATION_QEMU_X86_Q35)
/*
* Qemu has the fw_cfg interface at 0x510. Move the pmbase to a
* non-conflicting address. No need to worry about speedstep, it
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index db5d3a641a..79a1a1d03f 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -370,7 +370,7 @@ static void enable_clock_gating(void)
RCBA32(0x38c0) |= 7;
}
-#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+#if CONFIG(HAVE_SMI_HANDLER)
static void i82801ix_lock_smm(struct device *dev)
{
#if TEST_SMM_FLASH_LOCKDOWN
@@ -394,7 +394,7 @@ static void i82801ix_lock_smm(struct device *dev)
/* Don't allow evil boot loaders, kernels, or
* userspace applications to deceive us:
*/
- if (!IS_ENABLED(CONFIG_PARALLEL_MP))
+ if (!CONFIG(PARALLEL_MP))
smm_lock();
#if TEST_SMM_FLASH_LOCKDOWN
@@ -466,7 +466,7 @@ static void lpc_init(struct device *dev)
/* Interrupt 9 should be level triggered (SCI) */
i8259_configure_irq_trigger(9, 1);
-#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+#if CONFIG(HAVE_SMI_HANDLER)
i82801ix_lock_smm(dev);
#endif
}
diff --git a/src/southbridge/intel/i82801jx/acpi/sleepstates.asl b/src/southbridge/intel/i82801jx/acpi/sleepstates.asl
index d7fb2a56bb..79818a109a 100644
--- a/src/southbridge/intel/i82801jx/acpi/sleepstates.asl
+++ b/src/southbridge/intel/i82801jx/acpi/sleepstates.asl
@@ -15,7 +15,7 @@
*/
Name(\_S0, Package(){0x0,0x0,0x0,0x0})
-#if !IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+#if !CONFIG(HAVE_ACPI_RESUME)
Name(\_S1, Package(){0x1,0x0,0x0,0x0})
#else
Name(\_S3, Package(){0x5,0x0,0x0,0x0})
diff --git a/src/southbridge/intel/i82801jx/i82801jx.c b/src/southbridge/intel/i82801jx/i82801jx.c
index d15f0e3556..ec5576d381 100644
--- a/src/southbridge/intel/i82801jx/i82801jx.c
+++ b/src/southbridge/intel/i82801jx/i82801jx.c
@@ -223,7 +223,7 @@ static void i82801jx_init(void *chip_info)
i82801jx_hide_functions();
/* Reset watchdog timer. */
-#if !IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+#if !CONFIG(HAVE_SMI_HANDLER)
outw(0x0008, DEFAULT_TCOBASE + 0x12); /* Set higher timer value. */
#endif
outw(0x0000, DEFAULT_TCOBASE + 0x00); /* Update timer. */
diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c
index f157fa5f61..a365825e7b 100644
--- a/src/southbridge/intel/i82801jx/lpc.c
+++ b/src/southbridge/intel/i82801jx/lpc.c
@@ -372,7 +372,7 @@ static void enable_clock_gating(void)
RCBA32(0x38c0) |= 7;
}
-#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+#if CONFIG(HAVE_SMI_HANDLER)
static void i82801jx_lock_smm(struct device *dev)
{
#if TEST_SMM_FLASH_LOCKDOWN
@@ -463,7 +463,7 @@ static void lpc_init(struct device *dev)
/* Interrupt 9 should be level triggered (SCI) */
i8259_configure_irq_trigger(9, 1);
-#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+#if CONFIG(HAVE_SMI_HANDLER)
i82801jx_lock_smm(dev);
#endif
}
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 51b44381de..d440f65eee 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -74,7 +74,7 @@ static void pch_enable_serial_irqs(struct device *dev)
/* Set packet length and toggle silent mode bit for one frame. */
pci_write_config8(dev, SERIRQ_CNTL,
(1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
-#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)
+#if !CONFIG(SERIRQ_CONTINUOUS_MODE)
pci_write_config8(dev, SERIRQ_CNTL,
(1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
#endif
@@ -283,7 +283,7 @@ static void pch_rtc_init(struct device *dev)
if (rtc_failed) {
reg8 &= ~RTC_BATTERY_DEAD;
pci_write_config8(dev, GEN_PMCON_3, reg8);
-#if IS_ENABLED(CONFIG_ELOG)
+#if CONFIG(ELOG)
elog_add_event(ELOG_TYPE_RTC_RESET);
#endif
}
@@ -798,8 +798,8 @@ static void southbridge_fill_ssdt(struct device *device)
static void lpc_final(struct device *dev)
{
/* Call SMM finalize() handlers before resume */
- if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
- if (IS_ENABLED(CONFIG_INTEL_CHIPSET_LOCKDOWN) ||
+ if (CONFIG(HAVE_SMI_HANDLER)) {
+ if (CONFIG(INTEL_CHIPSET_LOCKDOWN) ||
acpi_is_wakeup_s3()) {
outb(APM_CNT_FINALIZE, APM_CNT);
}
diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c
index d774f80f03..df224d364e 100644
--- a/src/southbridge/intel/ibexpeak/me.c
+++ b/src/southbridge/intel/ibexpeak/me.c
@@ -40,7 +40,7 @@
#include "me.h"
#include "pch.h"
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
#include <vendorcode/google/chromeos/gnvs.h>
#endif
@@ -59,7 +59,7 @@ static const char *me_bios_path_values[] = {
/* MMIO base address for MEI interface */
static u32 *mei_base_address;
-#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
+#if CONFIG(DEBUG_INTEL_ME)
static void mei_dump(void *ptr, int dword, int offset, const char *type)
{
struct mei_csr *csr;
@@ -470,7 +470,7 @@ static me_bios_path intel_me_path(struct device *dev)
if (hfs.error_code || hfs.fpt_bad)
path = ME_ERROR_BIOS_PATH;
-#if IS_ENABLED(CONFIG_ELOG)
+#if CONFIG(ELOG)
if (path != ME_NORMAL_BIOS_PATH) {
struct elog_event_data_me_extended data = {
.current_working_state = hfs.working_state,
@@ -559,7 +559,7 @@ static int intel_me_extend_valid(struct device *dev)
}
printk(BIOS_DEBUG, "\n");
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
/* Save hash in NVS for the OS to verify */
chromeos_set_me_hash(extend, count);
#endif
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index 13579460dc..9b2dd8ac8e 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -62,7 +62,7 @@ int pch_silicon_type(void);
int pch_silicon_supported(int type, int rev);
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
void gpi_route_interrupt(u8 gpi, u8 mode);
-#if IS_ENABLED(CONFIG_ELOG)
+#if CONFIG(ELOG)
void pch_log_state(void);
#endif
#else /* __PRE_RAM__ */
diff --git a/src/southbridge/intel/ibexpeak/smi.c b/src/southbridge/intel/ibexpeak/smi.c
index d9d021571f..7de8b3b995 100644
--- a/src/southbridge/intel/ibexpeak/smi.c
+++ b/src/southbridge/intel/ibexpeak/smi.c
@@ -228,7 +228,7 @@ void southbridge_smm_init(void)
u16 pm1_en;
u32 gpe0_en;
-#if IS_ENABLED(CONFIG_ELOG)
+#if CONFIG(ELOG)
/* Log events from chipset before clearing */
pch_log_state();
#endif
diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c
index e6e4682057..fabe1c41ba 100644
--- a/src/southbridge/intel/ibexpeak/smihandler.c
+++ b/src/southbridge/intel/ibexpeak/smihandler.c
@@ -430,7 +430,7 @@ static void southbridge_smi_sleep(void)
/* Do any mainboard sleep handling */
mainboard_smi_sleep(slp_typ);
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
/* Log S3, S4, and S5 entry */
if (slp_typ >= ACPI_S3)
elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
@@ -532,7 +532,7 @@ static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd)
return NULL;
}
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
static void southbridge_smi_gsmi(void)
{
u32 *ret, *param;
@@ -604,7 +604,7 @@ static void southbridge_smi_apmc(void)
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}
break;
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
case APM_CNT_ELOG_GSMI:
southbridge_smi_gsmi();
break;
@@ -628,7 +628,7 @@ static void southbridge_smi_pm1(void)
// power button pressed
u32 reg32;
reg32 = (7 << 10) | (1 << 13);
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
elog_add_event(ELOG_TYPE_POWER_BUTTON);
#endif
outl(reg32, pmbase + PM1_CNT);
diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl
index a25282a390..90ff02d1f1 100644
--- a/src/southbridge/intel/lynxpoint/acpi/pch.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl
@@ -96,7 +96,7 @@ Scope(\)
#include "smbus.asl"
// Serial IO
-#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP)
+#if CONFIG(INTEL_LYNXPOINT_LP)
#include "serialio.asl"
#include "lpt_lp.asl"
#endif
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index a5c69e050c..994021c6b0 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -23,7 +23,7 @@
#include "pch.h"
#include "chip.h"
-#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP)
+#if CONFIG(INTEL_LYNXPOINT_LP)
#include "lp_gpio.h"
#else
#include <southbridge/intel/common/gpio.h>
@@ -127,7 +127,7 @@ int early_pch_init(const void *gpio_map,
pch_enable_bars();
-#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP)
+#if CONFIG(INTEL_LYNXPOINT_LP)
setup_pch_lp_gpios(gpio_map);
#else
setup_pch_gpios(gpio_map);
@@ -150,7 +150,7 @@ int early_pch_init(const void *gpio_map,
wake_from_s3 = sleep_type_s3();
-#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
+#if CONFIG(ELOG_BOOT_COUNT)
if (!wake_from_s3)
boot_count_increment();
#endif
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 59074e09e6..94b3111d1e 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -82,7 +82,7 @@ static void pch_enable_serial_irqs(struct device *dev)
/* Set packet length and toggle silent mode bit for one frame. */
pci_write_config8(dev, SERIRQ_CNTL,
(1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
-#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)
+#if !CONFIG(SERIRQ_CONTINUOUS_MODE)
pci_write_config8(dev, SERIRQ_CNTL,
(1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
#endif
@@ -490,7 +490,7 @@ static void enable_lp_clock_gating(struct device *dev)
static void pch_set_acpi_mode(void)
{
-#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+#if CONFIG(HAVE_SMI_HANDLER)
if (!acpi_is_wakeup_s3()) {
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
@@ -754,7 +754,7 @@ static void southbridge_inject_dsdt(struct device *dev)
gnvs->mpen = 1; /* Enable Multi Processing */
gnvs->pcnt = dev_count_cpu();
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
chromeos_init_chromeos_acpi(&(gnvs->chromeos));
#endif
@@ -976,7 +976,7 @@ static void lpc_final(struct device *dev)
RCBA32(0x3898) = SPI_OPMENU_LOWER;
RCBA32(0x389c) = SPI_OPMENU_UPPER;
- if (acpi_is_wakeup_s3() || IS_ENABLED(CONFIG_INTEL_CHIPSET_LOCKDOWN))
+ if (acpi_is_wakeup_s3() || CONFIG(INTEL_CHIPSET_LOCKDOWN))
outb(APM_CNT_FINALIZE, APM_CNT);
}
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c
index 450091c623..f5f94fe625 100644
--- a/src/southbridge/intel/lynxpoint/me_9.x.c
+++ b/src/southbridge/intel/lynxpoint/me_9.x.c
@@ -38,7 +38,7 @@
#include "me.h"
#include "pch.h"
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
#include <vendorcode/google/chromeos/chromeos.h>
#include <vendorcode/google/chromeos/gnvs.h>
#endif
@@ -64,7 +64,7 @@ void intel_me_mbp_clear(pci_devfn_t dev);
void intel_me_mbp_clear(struct device *dev);
#endif
-#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
+#if CONFIG(DEBUG_INTEL_ME)
static void mei_dump(void *ptr, int dword, int offset, const char *type)
{
struct mei_csr *csr;
@@ -378,7 +378,7 @@ static int mei_recv_msg(void *header, int header_bytes,
return mei_wait_for_me_ready();
}
-#if IS_ENABLED (CONFIG_DEBUG_INTEL_ME) || defined(__SMM__)
+#if CONFIG(DEBUG_INTEL_ME) || defined(__SMM__)
static inline int mei_sendrecv_mkhi(struct mkhi_header *mkhi,
void *req_data, int req_bytes,
void *rsp_data, int rsp_bytes)
@@ -480,7 +480,7 @@ static void me_print_fw_version(mbp_fw_version_name *vers_name)
vers_name->hotfix_version, vers_name->build_version);
}
-#if IS_ENABLED (CONFIG_DEBUG_INTEL_ME)
+#if CONFIG(DEBUG_INTEL_ME)
static inline void print_cap(const char *name, int state)
{
printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n",
@@ -536,7 +536,7 @@ static void me_print_fwcaps(mbp_mefwcaps *cap)
#endif /* CONFIG_DEBUG_INTEL_ME */
#endif
-#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */
+#if CONFIG(CHROMEOS) && 0 /* DISABLED */
/* Tell ME to issue a global reset */
static int mkhi_global_reset(void)
{
@@ -596,7 +596,7 @@ void intel_me_finalize_smm(void)
if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0)
return;
-#if IS_ENABLED(CONFIG_ME_MBP_CLEAR_LATE)
+#if CONFIG(ME_MBP_CLEAR_LATE)
/* Wait for ME MBP Cleared indicator */
intel_me_mbp_clear(PCH_ME_DEV);
#endif
@@ -723,7 +723,7 @@ static me_bios_path intel_me_path(struct device *dev)
path = ME_ERROR_BIOS_PATH;
}
-#if IS_ENABLED(CONFIG_ELOG)
+#if CONFIG(ELOG)
if (path != ME_NORMAL_BIOS_PATH) {
struct elog_event_data_me_extended data = {
.current_working_state = hfs.working_state,
@@ -812,7 +812,7 @@ static int intel_me_extend_valid(struct device *dev)
}
printk(BIOS_DEBUG, "\n");
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
/* Save hash in NVS for the OS to verify */
chromeos_set_me_hash(extend, count);
#endif
@@ -851,7 +851,7 @@ static void intel_me_init(struct device *dev)
#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG)
me_print_fw_version(mbp_data.fw_version_name);
-#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
+#if CONFIG(DEBUG_INTEL_ME)
me_print_fwcaps(mbp_data.fw_capabilities);
#endif
@@ -1008,7 +1008,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev)
host.interrupt_generate = 1;
write_host_csr(&host);
-#if !IS_ENABLED(CONFIG_ME_MBP_CLEAR_LATE)
+#if !CONFIG(ME_MBP_CLEAR_LATE)
/* Wait for the mbp_cleared indicator. */
intel_me_mbp_clear(dev);
#endif
@@ -1017,7 +1017,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev)
#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG)
printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n",
mbp->header.num_entries, mbp->header.mbp_size);
-#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
+#if CONFIG(DEBUG_INTEL_ME)
for (i = 0; i < mbp->header.mbp_size - 1; i++) {
printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]);
}
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 026fcdd383..97d0aa33b3 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -72,7 +72,7 @@
#define SMBUS_IO_BASE 0x0400
#define SMBUS_SLAVE_ADDR 0x24
-#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP)
+#if CONFIG(INTEL_LYNXPOINT_LP)
#define DEFAULT_PMBASE 0x1000
#define DEFAULT_GPIOBASE 0x1400
#define DEFAULT_GPIOSIZE 0x400
@@ -177,7 +177,7 @@ void pch_disable_devfn(struct device *dev);
u32 pch_iobp_read(u32 address);
void pch_iobp_write(u32 address, u32 data);
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
-#if IS_ENABLED(CONFIG_ELOG)
+#if CONFIG(ELOG)
void pch_log_state(void);
#endif
void acpi_create_intel_hpet(acpi_hpet_t * hpet);
diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c
index b14c1f7c91..3c63723f72 100644
--- a/src/southbridge/intel/lynxpoint/pmutil.c
+++ b/src/southbridge/intel/lynxpoint/pmutil.c
@@ -26,7 +26,7 @@
#include <console/console.h>
#include "pch.h"
-#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP)
+#if CONFIG(INTEL_LYNXPOINT_LP)
#include "lp_gpio.h"
#endif
diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c
index cf70d21ad9..426fb4233d 100644
--- a/src/southbridge/intel/lynxpoint/smi.c
+++ b/src/southbridge/intel/lynxpoint/smi.c
@@ -28,7 +28,7 @@ void southbridge_smm_clear_state(void)
{
u32 smi_en;
-#if IS_ENABLED(CONFIG_ELOG)
+#if CONFIG(ELOG)
/* Log events from chipset before clearing */
pch_log_state();
#endif
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index 8c46ab0255..bfa112a807 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -135,13 +135,13 @@ static void southbridge_smi_sleep(void)
mainboard_smi_sleep(slp_typ);
/* USB sleep preparations */
-#if !IS_ENABLED(CONFIG_FINALIZE_USB_ROUTE_XHCI)
+#if !CONFIG(FINALIZE_USB_ROUTE_XHCI)
usb_ehci_sleep_prepare(PCH_EHCI1_DEV, slp_typ);
usb_ehci_sleep_prepare(PCH_EHCI2_DEV, slp_typ);
#endif
usb_xhci_sleep_prepare(PCH_XHCI_DEV, slp_typ);
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
/* Log S3, S4, and S5 entry */
if (slp_typ >= ACPI_S3)
elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
@@ -248,7 +248,7 @@ static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd)
return NULL;
}
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
static void southbridge_smi_gsmi(void)
{
u32 *ret, *param;
@@ -333,7 +333,7 @@ static void southbridge_smi_apmc(void)
case 0xca:
usb_xhci_route_all();
break;
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
case APM_CNT_ELOG_GSMI:
southbridge_smi_gsmi();
break;
@@ -352,7 +352,7 @@ static void southbridge_smi_pm1(void)
*/
if (pm1_sts & PWRBTN_STS) {
// power button pressed
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
elog_add_event(ELOG_TYPE_POWER_BUTTON);
#endif
disable_pm1_control(-1UL);