4 files changed, 73 insertions, 1 deletions
diff --git a/src/southbridge/intel/i82371eb/Kconfig b/src/southbridge/intel/i82371eb/Kconfig
index 9b037feb0e..3b5679657f 100644
--- a/src/southbridge/intel/i82371eb/Kconfig
+++ b/src/southbridge/intel/i82371eb/Kconfig
@@ -1,6 +1,7 @@
 config SOUTHBRIDGE_INTEL_I82371EB
 	bool
 	select TINY_BOOTBLOCK
+	select HAVE_ACPI_RESUME if HAVE_ACPI_TABLES
 
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
diff --git a/src/southbridge/intel/i82371eb/Makefile.inc b/src/southbridge/intel/i82371eb/Makefile.inc
index 940a17d2b5..9e2c3ebed9 100644
--- a/src/southbridge/intel/i82371eb/Makefile.inc
+++ b/src/southbridge/intel/i82371eb/Makefile.inc
@@ -26,6 +26,7 @@ driver-y +=  smbus.c
 driver-y +=  reset.c
 driver-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c
 driver-$(CONFIG_GENERATE_ACPI_TABLES) += acpi_tables.c
+driver-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.c
 
 romstage-y += early_pm.c
 romstage-y += early_smbus.c
diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c
index b1a51c6a8a..65af02abb0 100644
--- a/src/southbridge/intel/i82371eb/smbus.c
+++ b/src/southbridge/intel/i82371eb/smbus.c
@@ -31,6 +31,11 @@
 #include "i82371eb.h"
 #include "smbus.h"
 
+#if CONFIG_HAVE_ACPI_RESUME == 1
+extern u8 acpi_slp_type;
+int acpi_get_sleep_type(void);
+#endif
+
 static void pwrmgt_enable(struct device *dev)
 {
 	struct southbridge_intel_i82371eb_config *sb = dev->chip_info;
@@ -87,7 +92,13 @@ static void pwrmgt_enable(struct device *dev)
 	outw(0xffff,     DEFAULT_PMBASE + GLBSTS);
 	outl(0xffffffff, DEFAULT_PMBASE + DEVSTS);
 
-	/* set pmcntrl default */
+#if CONFIG_HAVE_ACPI_RESUME == 1
+	/* this reads PMCNTRL, so we have to call it before writing the
+	 * default value */
+	acpi_slp_type = acpi_get_sleep_type();
+#endif
+
+	/* set PMCNTRL default */
 	outw(SUS_TYP_S0|SCI_EN, DEFAULT_PMBASE + PMCNTRL);
 }
 
diff --git a/src/southbridge/intel/i82371eb/wakeup.c b/src/southbridge/intel/i82371eb/wakeup.c
new file mode 100644
index 0000000000..f018ad9adf
--- /dev/null
+++ b/src/southbridge/intel/i82371eb/wakeup.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include "i82371eb.h"
+
+int acpi_get_sleep_type(void);
+
+/*
+ * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142
+ *
+ * 0: soft off/suspend to disk					S5
+ * 1: suspend to ram						S3
+ * 2: powered on suspend, context lost				S2
+ *    Note: 'context lost' means the CPU restarts at the reset
+ *          vector
+ * 3: powered on suspend, CPU context lost			S1
+ *    Note: Looks like 'CPU context lost' does _not_ mean the
+ *          CPU restarts at the reset vector. Most likely only
+ *          caches are lost, so both 0x3 and 0x4 map to acpi S1
+ * 4: powered on suspend, context maintained			S1
+ * 5: working (clock control)					S0
+ * 6: reserved
+ * 7: reserved
+ */
+static const u8 acpi_sus_to_slp_typ[8] = {
+	5, 3, 2, 1, 1, 0, 0, 0
+};
+
+int acpi_get_sleep_type(void)
+{
+	u16 reg, result;
+
+	reg = inw(DEFAULT_PMBASE + PMCNTRL);
+	result = acpi_sus_to_slp_typ[(reg >> 10) & 7];
+
+	printk(BIOS_DEBUG, "Wakeup from ACPI sleep type S%d (PMCNTRL=%04x)\n", result, reg);
+
+	return result;
+}