diff options
Diffstat (limited to 'src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c')
| -rw-r--r-- | src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c b/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c index f1f5c2ab11..e0b293c81a 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c +++ b/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c @@ -22,8 +22,11 @@ */ #include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> #include <usbdebug.h> #include <device/pci_def.h> +#include "mcp55.h" #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE @@ -31,10 +34,6 @@ #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif -#define EHCI_BAR 0xFEF00000 /* EHCI BAR address */ -#define EHCI_BAR_INDEX 0x10 -#define EHCI_DEBUG_OFFSET 0x98 - void set_debug_port(unsigned int port) { u32 dword; @@ -47,7 +46,7 @@ void set_debug_port(unsigned int port) pci_write_config32(dev, 0x74, dword); } -static void mcp55_enable_usbdebug(unsigned int port) +void mcp55_enable_usbdebug(unsigned int port) { device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */ @@ -55,7 +54,7 @@ static void mcp55_enable_usbdebug(unsigned int port) set_debug_port(port); /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); |