summaryrefslogtreecommitdiff
path: root/src/southbridge/nvidia/mcp55
diff options
context:
space:
mode:
Diffstat (limited to 'src/southbridge/nvidia/mcp55')
-rw-r--r--src/southbridge/nvidia/mcp55/early_ctrl.c2
-rw-r--r--src/southbridge/nvidia/mcp55/early_setup_car.c38
-rw-r--r--src/southbridge/nvidia/mcp55/early_smbus.c20
-rw-r--r--src/southbridge/nvidia/mcp55/fadt.c2
-rw-r--r--src/southbridge/nvidia/mcp55/mcp55.c10
-rw-r--r--src/southbridge/nvidia/mcp55/mcp55.h18
-rw-r--r--src/southbridge/nvidia/mcp55/nic.c6
-rw-r--r--src/southbridge/nvidia/mcp55/smbus.c10
-rw-r--r--src/southbridge/nvidia/mcp55/smbus.h14
9 files changed, 60 insertions, 60 deletions
diff --git a/src/southbridge/nvidia/mcp55/early_ctrl.c b/src/southbridge/nvidia/mcp55/early_ctrl.c
index 092280b4af..042dfa0b0f 100644
--- a/src/southbridge/nvidia/mcp55/early_ctrl.c
+++ b/src/southbridge/nvidia/mcp55/early_ctrl.c
@@ -38,7 +38,7 @@ void do_board_reset(void)
outb(0x0e, 0x0cf9);
}
-void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
+void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn)
{
/* The default value for MCP55 is good. */
/* Set VFSMAF (VID/FID System Management Action Field) to 2. */
diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c
index 69d12bfad7..85198ad7c3 100644
--- a/src/southbridge/nvidia/mcp55/early_setup_car.c
+++ b/src/southbridge/nvidia/mcp55/early_setup_car.c
@@ -21,21 +21,21 @@
#include <device/pci_ops.h>
#ifdef UNUSED_CODE
-int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned vendorid, unsigned val);
+int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned int vendorid, unsigned int val);
static int set_ht_link_mcp55(u8 ht_c_num)
{
- unsigned vendorid = 0x10de;
- unsigned val = 0x01610109;
+ unsigned int vendorid = 0x10de;
+ unsigned int val = 0x01610109;
/* NVIDIA MCP55 hardcode, hardware can not set it automatically. */
return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val);
}
-static void setup_ss_table(unsigned index, unsigned where, unsigned control,
+static void setup_ss_table(unsigned int index, unsigned int where, unsigned int control,
const unsigned int *register_values, int max)
{
int i;
- unsigned val;
+ unsigned int val;
val = inl(control);
val &= 0xfffffffe;
@@ -82,8 +82,8 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control,
*/
#define MCP55_DEV(d, f, r) PCI_ADDR(0, d, f, r)
-static void mcp55_early_set_port(unsigned mcp55_num, unsigned *busn,
- unsigned *devn, unsigned *io_base)
+static void mcp55_early_set_port(unsigned int mcp55_num, unsigned int *busn,
+ unsigned int *devn, unsigned int *io_base)
{
static const unsigned int ctrl_devport_conf[] = {
@@ -100,8 +100,8 @@ static void mcp55_early_set_port(unsigned mcp55_num, unsigned *busn,
}
}
-static void mcp55_early_clear_port(unsigned mcp55_num, unsigned *busn,
- unsigned *devn, unsigned *io_base)
+static void mcp55_early_clear_port(unsigned int mcp55_num, unsigned int *busn,
+ unsigned int *devn, unsigned int *io_base)
{
static const unsigned int ctrl_devport_conf_clear[] = {
MCP55_DEV(1, 1, ANACTRL_REG_POS), ~(0x0000ff00), 0,
@@ -117,8 +117,8 @@ static void mcp55_early_clear_port(unsigned mcp55_num, unsigned *busn,
}
}
-static void mcp55_early_pcie_setup(unsigned busnx, unsigned devnx,
- unsigned anactrl_io_base, unsigned pci_e_x)
+static void mcp55_early_pcie_setup(unsigned int busnx, unsigned int devnx,
+ unsigned int anactrl_io_base, unsigned int pci_e_x)
{
u32 tgio_ctrl, pll_ctrl, dword;
int i;
@@ -156,9 +156,9 @@ static void mcp55_early_pcie_setup(unsigned busnx, unsigned devnx,
mdelay(100); /* Need to wait 100ms. */
}
-static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn,
- unsigned *devn, unsigned *io_base,
- unsigned *pci_e_x)
+static void mcp55_early_setup(unsigned int mcp55_num, unsigned int *busn,
+ unsigned int *devn, unsigned int *io_base,
+ unsigned int *pci_e_x)
{
static const unsigned int ctrl_conf_1[] = {
RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x10, 0x0007ffff, 0xff78000,
@@ -348,21 +348,21 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn,
static int mcp55_early_setup_x(void)
{
/* Find out how many MCP55 we have. */
- unsigned busn[HT_CHAIN_NUM_MAX] = {0};
- unsigned devn[HT_CHAIN_NUM_MAX] = {0};
- unsigned io_base[HT_CHAIN_NUM_MAX] = {0};
+ unsigned int busn[HT_CHAIN_NUM_MAX] = {0};
+ unsigned int devn[HT_CHAIN_NUM_MAX] = {0};
+ unsigned int io_base[HT_CHAIN_NUM_MAX] = {0};
/*
* FIXME: May have problem if there is different MCP55 HTX card with
* different PCI_E lane allocation. Need to use same trick about
* pci1234 to verify node/link connection.
*/
- unsigned pci_e_x[HT_CHAIN_NUM_MAX] = {
+ unsigned int pci_e_x[HT_CHAIN_NUM_MAX] = {
CONFIG_MCP55_PCI_E_X_0, CONFIG_MCP55_PCI_E_X_1,
CONFIG_MCP55_PCI_E_X_2, CONFIG_MCP55_PCI_E_X_3,
};
int mcp55_num = 0, ht_c_index;
- unsigned busnx, devnx;
+ unsigned int busnx, devnx;
/* FIXME: Multi PCI segment handling. */
diff --git a/src/southbridge/nvidia/mcp55/early_smbus.c b/src/southbridge/nvidia/mcp55/early_smbus.c
index fe9ccdd746..1b49456a18 100644
--- a/src/southbridge/nvidia/mcp55/early_smbus.c
+++ b/src/southbridge/nvidia/mcp55/early_smbus.c
@@ -48,48 +48,48 @@ void enable_smbus(void)
outb(inb(SMBUS1_IO_BASE + SMBHSTSTAT), SMBUS1_IO_BASE + SMBHSTSTAT);
}
-int smbus_recv_byte(unsigned device)
+int smbus_recv_byte(unsigned int device)
{
return do_smbus_recv_byte(SMBUS0_IO_BASE, device);
}
-int smbus_send_byte(unsigned device, unsigned char val)
+int smbus_send_byte(unsigned int device, unsigned char val)
{
return do_smbus_send_byte(SMBUS0_IO_BASE, device, val);
}
-int smbus_read_byte(unsigned device, unsigned address)
+int smbus_read_byte(unsigned int device, unsigned int address)
{
return do_smbus_read_byte(SMBUS0_IO_BASE, device, address);
}
-int smbus_write_byte(unsigned device, unsigned address,
+int smbus_write_byte(unsigned int device, unsigned int address,
unsigned char val)
{
return do_smbus_write_byte(SMBUS0_IO_BASE, device, address, val);
}
-int smbusx_recv_byte(unsigned smb_index, unsigned device)
+int smbusx_recv_byte(unsigned int smb_index, unsigned int device)
{
return do_smbus_recv_byte(SMBUS0_IO_BASE + (smb_index << 8), device);
}
-int smbusx_send_byte(unsigned smb_index, unsigned device,
+int smbusx_send_byte(unsigned int smb_index, unsigned int device,
unsigned char val)
{
return do_smbus_send_byte(SMBUS0_IO_BASE + (smb_index << 8),
device, val);
}
-int smbusx_read_byte(unsigned smb_index, unsigned device,
- unsigned address)
+int smbusx_read_byte(unsigned int smb_index, unsigned int device,
+ unsigned int address)
{
return do_smbus_read_byte(SMBUS0_IO_BASE + (smb_index << 8),
device, address);
}
-int smbusx_write_byte(unsigned smb_index, unsigned device,
- unsigned address, unsigned char val)
+int smbusx_write_byte(unsigned int smb_index, unsigned int device,
+ unsigned int address, unsigned char val)
{
return do_smbus_write_byte(SMBUS0_IO_BASE + (smb_index << 8),
device, address, val);
diff --git a/src/southbridge/nvidia/mcp55/fadt.c b/src/southbridge/nvidia/mcp55/fadt.c
index 9a70ba1a98..16f0df85de 100644
--- a/src/southbridge/nvidia/mcp55/fadt.c
+++ b/src/southbridge/nvidia/mcp55/fadt.c
@@ -23,7 +23,7 @@
#include <device/pci_ids.h>
#include <version.h>
-extern unsigned pm_base;
+extern unsigned int pm_base;
/* Create the Fixed ACPI Description Tables (FADT) for this board. */
void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
diff --git a/src/southbridge/nvidia/mcp55/mcp55.c b/src/southbridge/nvidia/mcp55/mcp55.c
index bd49d9be5f..db646cd659 100644
--- a/src/southbridge/nvidia/mcp55/mcp55.c
+++ b/src/southbridge/nvidia/mcp55/mcp55.c
@@ -25,7 +25,7 @@
static u32 final_reg;
-static struct device *find_lpc_dev(struct device *dev, unsigned devfn)
+static struct device *find_lpc_dev(struct device *dev, unsigned int devfn)
{
struct device *lpc_dev;
@@ -55,10 +55,10 @@ static struct device *find_lpc_dev(struct device *dev, unsigned devfn)
void mcp55_enable(struct device *dev)
{
struct device *lpc_dev = NULL, *sm_dev = NULL;
- unsigned index = 0, index2 = 0;
+ unsigned int index = 0, index2 = 0;
u32 reg_old, reg;
u8 byte;
- unsigned deviceid, vendorid, devfn;
+ unsigned int deviceid, vendorid, devfn;
int i;
if (dev->device == 0x0000) {
@@ -217,8 +217,8 @@ void mcp55_enable(struct device *dev)
}
}
-static void mcp55_set_subsystem(struct device *dev, unsigned vendor,
- unsigned device)
+static void mcp55_set_subsystem(struct device *dev, unsigned int vendor,
+ unsigned int device)
{
pci_write_config32(dev, 0x40,
((device & 0xffff) << 16) | (vendor & 0xffff));
diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h
index ac689094ca..c3e93d3714 100644
--- a/src/southbridge/nvidia/mcp55/mcp55.h
+++ b/src/southbridge/nvidia/mcp55/mcp55.h
@@ -30,19 +30,19 @@ void mcp55_enable(struct device *dev);
extern struct pci_operations mcp55_pci_ops;
#endif
-void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
+void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn);
void enable_smbus(void);
/* Concflict declarations with <device/smbus.h>. */
#if !ENV_RAMSTAGE
-int smbus_recv_byte(unsigned device);
-int smbus_send_byte(unsigned device, unsigned char val);
-int smbus_read_byte(unsigned device, unsigned address);
-int smbus_write_byte(unsigned device, unsigned address, unsigned char val);
-int smbusx_recv_byte(unsigned smb_index, unsigned device);
-int smbusx_send_byte(unsigned smb_index, unsigned device, unsigned char val);
-int smbusx_read_byte(unsigned smb_index, unsigned device, unsigned address);
-int smbusx_write_byte(unsigned smb_index, unsigned device, unsigned address,
+int smbus_recv_byte(unsigned int device);
+int smbus_send_byte(unsigned int device, unsigned char val);
+int smbus_read_byte(unsigned int device, unsigned int address);
+int smbus_write_byte(unsigned int device, unsigned int address, unsigned char val);
+int smbusx_recv_byte(unsigned int smb_index, unsigned int device);
+int smbusx_send_byte(unsigned int smb_index, unsigned int device, unsigned char val);
+int smbusx_read_byte(unsigned int smb_index, unsigned int device, unsigned int address);
+int smbusx_write_byte(unsigned int smb_index, unsigned int device, unsigned int address,
unsigned char val);
#endif /* !ENV_RAMSTAGE */
diff --git a/src/southbridge/nvidia/mcp55/nic.c b/src/southbridge/nvidia/mcp55/nic.c
index af4df44293..9e350dda26 100644
--- a/src/southbridge/nvidia/mcp55/nic.c
+++ b/src/southbridge/nvidia/mcp55/nic.c
@@ -29,10 +29,10 @@
#include "chip.h"
#include "mcp55.h"
-static int phy_read(u8 *base, unsigned phy_addr, unsigned phy_reg)
+static int phy_read(u8 *base, unsigned int phy_addr, unsigned int phy_reg)
{
u32 dword;
- unsigned loop = 0x100;
+ unsigned int loop = 0x100;
write32(base + 0x190, 0x8000); /* Clear MDIO lock bit. */
mdelay(1);
@@ -61,7 +61,7 @@ static void phy_detect(u8 *base)
{
u32 dword;
int i, val;
- unsigned id;
+ unsigned int id;
dword = read32(base + 0x188);
dword &= ~(1 << 20);
diff --git a/src/southbridge/nvidia/mcp55/smbus.c b/src/southbridge/nvidia/mcp55/smbus.c
index 37f4a1e3f1..0f8dbe3fc5 100644
--- a/src/southbridge/nvidia/mcp55/smbus.c
+++ b/src/southbridge/nvidia/mcp55/smbus.c
@@ -26,7 +26,7 @@
static int lsmbus_recv_byte(struct device *dev)
{
- unsigned device;
+ unsigned int device;
struct resource *res;
struct bus *pbus;
@@ -40,7 +40,7 @@ static int lsmbus_recv_byte(struct device *dev)
static int lsmbus_send_byte(struct device *dev, u8 val)
{
- unsigned device;
+ unsigned int device;
struct resource *res;
struct bus *pbus;
@@ -54,7 +54,7 @@ static int lsmbus_send_byte(struct device *dev, u8 val)
static int lsmbus_read_byte(struct device *dev, u8 address)
{
- unsigned device;
+ unsigned int device;
struct resource *res;
struct bus *pbus;
@@ -68,7 +68,7 @@ static int lsmbus_read_byte(struct device *dev, u8 address)
static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)
{
- unsigned device;
+ unsigned int device;
struct resource *res;
struct bus *pbus;
@@ -87,7 +87,7 @@ static struct smbus_bus_operations lops_smbus_bus = {
};
#if CONFIG(HAVE_ACPI_TABLES)
-unsigned pm_base;
+unsigned int pm_base;
#endif
static void mcp55_sm_read_resources(struct device *dev)
diff --git a/src/southbridge/nvidia/mcp55/smbus.h b/src/southbridge/nvidia/mcp55/smbus.h
index f2704525bb..91e48ba5fe 100644
--- a/src/southbridge/nvidia/mcp55/smbus.h
+++ b/src/southbridge/nvidia/mcp55/smbus.h
@@ -37,7 +37,7 @@ static inline void smbus_delay(void)
outb(0x80, 0x80);
}
-static int smbus_wait_until_done(unsigned smbus_io_base)
+static int smbus_wait_until_done(unsigned int smbus_io_base)
{
unsigned long loops;
loops = SMBUS_TIMEOUT;
@@ -52,7 +52,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
} while (--loops);
return -3;
}
-static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
+static int do_smbus_recv_byte(unsigned int smbus_io_base, unsigned int device)
{
unsigned char global_status_register;
unsigned char byte;
@@ -80,9 +80,9 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
}
return byte;
}
-static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val)
+static int do_smbus_send_byte(unsigned int smbus_io_base, unsigned int device, unsigned char val)
{
- unsigned global_status_register;
+ unsigned int global_status_register;
outb(val, smbus_io_base + SMBHSTDAT0);
smbus_delay();
@@ -110,7 +110,7 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned
}
return 0;
}
-static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
+static int do_smbus_read_byte(unsigned int smbus_io_base, unsigned int device, unsigned int address)
{
unsigned char global_status_register;
unsigned char byte;
@@ -142,9 +142,9 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned
}
-static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val)
+static int do_smbus_write_byte(unsigned int smbus_io_base, unsigned int device, unsigned int address, unsigned char val)
{
- unsigned global_status_register;
+ unsigned int global_status_register;
outb(val, smbus_io_base + SMBHSTDAT0);
smbus_delay();
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-11 03:03:44 +0000