diff options
Diffstat (limited to 'src/southbridge/nvidia/mcp55')
| -rw-r--r-- | src/southbridge/nvidia/mcp55/bootblock.c | 7 | ||||
| -rw-r--r-- | src/southbridge/nvidia/mcp55/early_setup_car.c | 19 | ||||
| -rw-r--r-- | src/southbridge/nvidia/mcp55/lpc.c | 14 | ||||
| -rw-r--r-- | src/southbridge/nvidia/mcp55/mcp55.c | 11 |
4 files changed, 1 insertions, 50 deletions
diff --git a/src/southbridge/nvidia/mcp55/bootblock.c b/src/southbridge/nvidia/mcp55/bootblock.c index b77463af7a..6d24f568da 100644 --- a/src/southbridge/nvidia/mcp55/bootblock.c +++ b/src/southbridge/nvidia/mcp55/bootblock.c @@ -28,13 +28,8 @@ static void mcp55_enable_rom(void) pci_devfn_t addr; /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ -#if 0 - /* Default MCP55 LPC single */ - addr = pci_locate_device(PCI_ID(0x10de, 0x0367), 0); -#else -// addr = pci_locate_device(PCI_ID(0x10de, 0x0360), 0); + addr = PCI_DEV(0, (MCP55_DEVN_BASE + 1), 0); -#endif /* Set the 15MB enable bits. */ byte = pci_read_config8(addr, 0x88); diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c index 76947ec18d..7f1d03b512 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/early_setup_car.c @@ -253,7 +253,6 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, #if CONFIG_MCP55_USE_AZA RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE, - // RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), ~(1 << 14), (1 << 14), #endif #ifdef MCP55_MB_SETUP @@ -326,22 +325,6 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, PCI_DEV(busn[j], devn[j], 0), io_base[j]); } -#if 0 - for (j = 0; j < mcp55_num; j++) { - // PCI-E (XSPLL) SS table 0x40, x044, 0x48 - // SATA (SPPLL) SS table 0xb0, 0xb4, 0xb8 - // CPU (PPLL) SS table 0xc0, 0xc4, 0xc8 - setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0x40, - io_base[j] + ANACTRL_IO_BASE + 0x44, - io_base[j] + ANACTRL_IO_BASE + 0x48, pcie_ss_tbl, 64); - setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xb0, - io_base[j] + ANACTRL_IO_BASE + 0xb4, - io_base[j] + ANACTRL_IO_BASE + 0xb8, sata_ss_tbl, 64); - setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xc0, - io_base[j] + ANACTRL_IO_BASE + 0xc4, - io_base[j] + ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64); - } -#endif } #ifndef HT_CHAIN_NUM_MAX @@ -405,7 +388,5 @@ out: mcp55_early_clear_port(mcp55_num, busn, devn, io_base); - // set_ht_link_mcp55(HT_CHAIN_NUM_MAX); - return 0; } diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 824abc526e..afc6e647b8 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -91,11 +91,6 @@ static void lpc_init(device_t dev) lpc_common_init(dev, 1); -#if 0 - /* Posted memory write enable. */ - byte = pci_read_config8(dev, 0x46); - pci_write_config8(dev, 0x46, byte | (1 << 0)); -#endif /* power after power fail */ #if 1 @@ -122,13 +117,6 @@ static void lpc_init(device_t dev) (on * 12) + (on >> 1), (on & 1) * 5); } -#if 0 - /* Enable Port 92 fast reset (default is enabled). */ - byte = pci_read_config8(dev, 0xe8); - byte |= ~(1 << 3); - pci_write_config8(dev, 0xe8, byte); -#endif - /* Enable error reporting. */ /* Set up sync flood detected. */ byte = pci_read_config8(dev, 0x47); @@ -258,7 +246,6 @@ static struct device_operations lpc_ops = { .enable_resources = mcp55_lpc_enable_resources, .init = lpc_init, .scan_bus = scan_lpc_bus, -// .enable = mcp55_enable, .ops_pci = &mcp55_pci_ops, }; static const unsigned short lpc_ids[] = { @@ -295,7 +282,6 @@ static struct device_operations lpc_slave_ops = { .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_slave_init, -// .enable = mcp55_enable, .ops_pci = &mcp55_pci_ops, }; diff --git a/src/southbridge/nvidia/mcp55/mcp55.c b/src/southbridge/nvidia/mcp55/mcp55.c index cfe5e175c9..7c43feac98 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.c +++ b/src/southbridge/nvidia/mcp55/mcp55.c @@ -68,9 +68,7 @@ void mcp55_enable(device_t dev) if (dev->device == 0x0000) { vendorid = pci_read_config32(dev, PCI_VENDOR_ID); deviceid = (vendorid >> 16) & 0xffff; -// vendorid &= 0xffff; } else { -// vendorid = dev->vendor; deviceid = dev->device; } @@ -200,15 +198,6 @@ void mcp55_enable(device_t dev) | (1 << 11) | (1 << 10) | (1 << 9)); pci_write_config32(sm_dev, 0xe8, final_reg); /* Enable all at first. */ -#if 0 - reg_old = reg = pci_read_config32(sm_dev, 0xe4); -// reg |= (1 << 0); - reg &= ~(0x3f << 4); - if (reg != reg_old) { - printk(BIOS_DEBUG, "mcp55.c pcie enabled\n"); - pci_write_config32(sm_dev, 0xe4, reg); - } -#endif } if (!dev->enabled) { |