diff options
Diffstat (limited to 'src/southbridge/nvidia/mcp55')
| -rw-r--r-- | src/southbridge/nvidia/mcp55/mcp55_aza.c | 2 | ||||
| -rw-r--r-- | src/southbridge/nvidia/mcp55/mcp55_lpc.c | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/nvidia/mcp55/mcp55_aza.c b/src/southbridge/nvidia/mcp55/mcp55_aza.c index cea0b49e8c..d4b0e8f2fb 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_aza.c +++ b/src/southbridge/nvidia/mcp55/mcp55_aza.c @@ -230,7 +230,7 @@ static void aza_init(struct device *dev) return; base =(uint8_t *) res->base; - printk(BIOS_DEBUG, "base = %08x\n", base); + printk(BIOS_DEBUG, "base = %p\n", base); codec_mask = codec_detect(base); diff --git a/src/southbridge/nvidia/mcp55/mcp55_lpc.c b/src/southbridge/nvidia/mcp55/mcp55_lpc.c index 869e8392e2..84612890e9 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_lpc.c +++ b/src/southbridge/nvidia/mcp55/mcp55_lpc.c @@ -80,7 +80,7 @@ static void enable_hpet(struct device *dev) pci_write_config32(dev,0x44, 0xfed00001); hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe; - printk(BIOS_DEBUG, "enabling HPET @0x%x\n", hpet_address); + printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address); } static void lpc_init(device_t dev) @@ -224,7 +224,7 @@ static void mcp55_lpc_enable_childrens_resources(device_t dev) if(!(res->flags & IORESOURCE_IO)) continue; base = res->base; end = resource_end(res); - printk(BIOS_DEBUG, "mcp55 lpc decode:%s, base=0x%08x, end=0x%08x\n",dev_path(child),base, end); + printk(BIOS_DEBUG, "mcp55 lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end); switch(base) { case 0x3f8: // COM1 reg |= (1<<0); break; |