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-rw-r--r--src/southbridge/nvidia/mcp55/Kconfig9
-rw-r--r--src/southbridge/nvidia/mcp55/Makefile.inc2
-rw-r--r--src/southbridge/nvidia/mcp55/mcp55.h1
-rw-r--r--src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c11
4 files changed, 17 insertions, 6 deletions
diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig
index 213b1755f9..6084b1ea44 100644
--- a/src/southbridge/nvidia/mcp55/Kconfig
+++ b/src/southbridge/nvidia/mcp55/Kconfig
@@ -6,3 +6,12 @@ config SOUTHBRIDGE_NVIDIA_MCP55
config ID_SECTION_OFFSET
hex
default 0x80 if SOUTHBRIDGE_NVIDIA_MCP55
+
+config EHCI_BAR
+ hex
+ default 0xfef00000 if SOUTHBRIDGE_NVIDIA_MCP55
+
+config EHCI_DEBUG_OFFSET
+ hex
+ default 0x98 if SOUTHBRIDGE_NVIDIA_MCP55
+
diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc
index 4388ca8e9a..a9dcf7f40f 100644
--- a/src/southbridge/nvidia/mcp55/Makefile.inc
+++ b/src/southbridge/nvidia/mcp55/Makefile.inc
@@ -15,5 +15,7 @@ driver-$(CONFIG_GENERATE_ACPI_TABLES) += mcp55_fadt.c
ramstage-y += mcp55_reset.c
+romstage-y += mcp55_enable_usbdebug.c
+
chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc
chipset_bootblock_lds += $(src)/southbridge/nvidia/mcp55/romstrap.lds
diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h
index 687232f302..acb291a1d0 100644
--- a/src/southbridge/nvidia/mcp55/mcp55.h
+++ b/src/southbridge/nvidia/mcp55/mcp55.h
@@ -29,4 +29,5 @@ void mcp55_enable(device_t dev);
#else
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
#endif
+void mcp55_enable_usbdebug(unsigned int port);
#endif /* MCP55_H */
diff --git a/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c b/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c
index f1f5c2ab11..e0b293c81a 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c
@@ -22,8 +22,11 @@
*/
#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
#include <usbdebug.h>
#include <device/pci_def.h>
+#include "mcp55.h"
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
@@ -31,10 +34,6 @@
#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
#endif
-#define EHCI_BAR 0xFEF00000 /* EHCI BAR address */
-#define EHCI_BAR_INDEX 0x10
-#define EHCI_DEBUG_OFFSET 0x98
-
void set_debug_port(unsigned int port)
{
u32 dword;
@@ -47,7 +46,7 @@ void set_debug_port(unsigned int port)
pci_write_config32(dev, 0x74, dword);
}
-static void mcp55_enable_usbdebug(unsigned int port)
+void mcp55_enable_usbdebug(unsigned int port)
{
device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */
@@ -55,7 +54,7 @@ static void mcp55_enable_usbdebug(unsigned int port)
set_debug_port(port);
/* Set the EHCI BAR address. */
- pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR);
+ pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
/* Enable access to the EHCI memory space registers. */
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);