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-rw-r--r--src/southbridge/nvidia/ck804/ck804_early_smbus.c4
-rw-r--r--src/southbridge/nvidia/ck804/ck804_lpc.c2
-rw-r--r--src/southbridge/nvidia/ck804/ck804_sata.c8
-rw-r--r--src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c2
-rw-r--r--src/southbridge/nvidia/mcp55/mcp55_early_smbus.c4
5 files changed, 10 insertions, 10 deletions
diff --git a/src/southbridge/nvidia/ck804/ck804_early_smbus.c b/src/southbridge/nvidia/ck804/ck804_early_smbus.c
index 2bf6732e79..db641415ff 100644
--- a/src/southbridge/nvidia/ck804/ck804_early_smbus.c
+++ b/src/southbridge/nvidia/ck804/ck804_early_smbus.c
@@ -12,9 +12,9 @@ static void enable_smbus(void)
device_t dev;
dev = pci_locate_device(PCI_ID(0x10de, 0x0052), 0);
if (dev == PCI_DEV_INVALID)
- die("SMBus controller not found\r\n");
+ die("SMBus controller not found\n");
- print_debug("SMBus controller enabled\r\n");
+ print_debug("SMBus controller enabled\n");
/* Set SMBus I/O base. */
pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
diff --git a/src/southbridge/nvidia/ck804/ck804_lpc.c b/src/southbridge/nvidia/ck804/ck804_lpc.c
index d68a5b1077..3458738f9b 100644
--- a/src/southbridge/nvidia/ck804/ck804_lpc.c
+++ b/src/southbridge/nvidia/ck804/ck804_lpc.c
@@ -250,7 +250,7 @@ static void ck804_lpc_enable_childrens_resources(device_t dev)
continue;
base = res->base;
end = resource_end(res);
- printk(BIOS_DEBUG, "ck804 lpc decode:%s, base=0x%08lx, end=0x%08lx\r\n", dev_path(child), base, end);
+ printk(BIOS_DEBUG, "ck804 lpc decode:%s, base=0x%08lx, end=0x%08lx\n", dev_path(child), base, end);
switch (base) {
case 0x3f8: // COM1
reg |= (1 << 0);
diff --git a/src/southbridge/nvidia/ck804/ck804_sata.c b/src/southbridge/nvidia/ck804/ck804_sata.c
index 8eed906ce8..2a29689ad6 100644
--- a/src/southbridge/nvidia/ck804/ck804_sata.c
+++ b/src/southbridge/nvidia/ck804/ck804_sata.c
@@ -51,7 +51,7 @@ static void sata_com_reset(struct device *dev, unsigned reset)
return;
dword = *(base + 0);
- printk(BIOS_DEBUG, "*(base+0)=%08x\r\n", dword);
+ printk(BIOS_DEBUG, "*(base+0)=%08x\n", dword);
if (dword == 0x113) {
loop = 200000; // 2
do {
@@ -60,11 +60,11 @@ static void sata_com_reset(struct device *dev, unsigned reset)
break;
udelay(10);
} while (--loop > 0);
- printk(BIOS_DEBUG, "loop=%d, *(base+4)=%08x\r\n", loop, dword);
+ printk(BIOS_DEBUG, "loop=%d, *(base+4)=%08x\n", loop, dword);
}
dword = *(base + 0x40);
- printk(BIOS_DEBUG, "*(base+0x40)=%08x\r\n", dword);
+ printk(BIOS_DEBUG, "*(base+0x40)=%08x\n", dword);
if (dword == 0x113) {
loop = 200000; //2
do {
@@ -73,7 +73,7 @@ static void sata_com_reset(struct device *dev, unsigned reset)
break;
udelay(10);
} while (--loop > 0);
- printk(BIOS_DEBUG, "loop=%d, *(base+0x44)=%08x\r\n", loop, dword);
+ printk(BIOS_DEBUG, "loop=%d, *(base+0x44)=%08x\n", loop, dword);
}
}
#endif
diff --git a/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c b/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
index cee5f25a24..6d776d38bd 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
@@ -412,7 +412,7 @@ static int mcp55_early_setup_x(void)
}
out:
- print_debug("mcp55_num:"); print_debug_hex8(mcp55_num); print_debug("\r\n");
+ print_debug("mcp55_num:"); print_debug_hex8(mcp55_num); print_debug("\n");
mcp55_early_set_port(mcp55_num, busn, devn, io_base);
mcp55_early_setup(mcp55_num, busn, devn, io_base, pci_e_x);
diff --git a/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c b/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c
index e27664aa18..83ea61965b 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c
@@ -33,10 +33,10 @@ static void enable_smbus(void)
dev = pci_locate_device(PCI_ID(0x10de, 0x0368), 0);
#if 0
if (dev == PCI_DEV_INVALID) {
- die("SMBUS controller not found\r\n");
+ die("SMBUS controller not found\n");
}
- print_debug("SMBus controller enabled\r\n");
+ print_debug("SMBus controller enabled\n");
#endif
/* set smbus iobase */
pci_write_config32(dev, 0x20, SMBUS0_IO_BASE | 1);