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-rw-r--r--src/southbridge/nvidia/ck804/Config.lb4
-rw-r--r--src/southbridge/nvidia/ck804/ck804_early_setup.c8
-rw-r--r--src/southbridge/nvidia/ck804/ck804_early_setup_car.c8
-rw-r--r--src/southbridge/nvidia/ck804/ck804_enable_rom.c6
-rw-r--r--src/southbridge/nvidia/ck804/ck804_lpc.c6
-rw-r--r--src/southbridge/nvidia/ck804/id.inc6
-rw-r--r--src/southbridge/nvidia/ck804/id.lds2
-rw-r--r--src/southbridge/nvidia/ck804/romstrap.lds2
-rw-r--r--src/southbridge/nvidia/mcp55/Config.lb4
-rw-r--r--src/southbridge/nvidia/mcp55/id.inc6
-rw-r--r--src/southbridge/nvidia/mcp55/id.lds2
-rw-r--r--src/southbridge/nvidia/mcp55/mcp55_enable_rom.c6
-rw-r--r--src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c6
-rw-r--r--src/southbridge/nvidia/mcp55/mcp55_lpc.c6
-rw-r--r--src/southbridge/nvidia/mcp55/mcp55_smbus.c4
-rw-r--r--src/southbridge/nvidia/mcp55/romstrap.lds2
16 files changed, 39 insertions, 39 deletions
diff --git a/src/southbridge/nvidia/ck804/Config.lb b/src/southbridge/nvidia/ck804/Config.lb
index 481ced004d..36682984e6 100644
--- a/src/southbridge/nvidia/ck804/Config.lb
+++ b/src/southbridge/nvidia/ck804/Config.lb
@@ -1,4 +1,4 @@
-uses HAVE_ACPI_TABLES
+uses CONFIG_HAVE_ACPI_TABLES
config chip.h
driver ck804.o
@@ -15,6 +15,6 @@ driver ck804_pcie.o
driver ck804_ht.o
object ck804_reset.o
-if HAVE_ACPI_TABLES
+if CONFIG_HAVE_ACPI_TABLES
object ck804_fadt.o
end
diff --git a/src/southbridge/nvidia/ck804/ck804_early_setup.c b/src/southbridge/nvidia/ck804/ck804_early_setup.c
index 0632197c7c..0d8a630d7a 100644
--- a/src/southbridge/nvidia/ck804/ck804_early_setup.c
+++ b/src/southbridge/nvidia/ck804/ck804_early_setup.c
@@ -71,13 +71,13 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control,
#define CK804_CHIP_REV 3
-#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
-#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE
+#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
+#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
#else
-#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE
+#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
#endif
-#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
+#if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
#define CK804B_DEVN_BASE 1
#else
#define CK804B_DEVN_BASE CK804_DEVN_BASE
diff --git a/src/southbridge/nvidia/ck804/ck804_early_setup_car.c b/src/southbridge/nvidia/ck804/ck804_early_setup_car.c
index cec869fae5..3e2a69a164 100644
--- a/src/southbridge/nvidia/ck804/ck804_early_setup_car.c
+++ b/src/southbridge/nvidia/ck804/ck804_early_setup_car.c
@@ -78,13 +78,13 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control,
#define CK804_CHIP_REV 3
-#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
-#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE
+#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
+#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
#else
-#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE
+#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
#endif
-#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
+#if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
#define CK804B_DEVN_BASE 1
#else
#define CK804B_DEVN_BASE CK804_DEVN_BASE
diff --git a/src/southbridge/nvidia/ck804/ck804_enable_rom.c b/src/southbridge/nvidia/ck804/ck804_enable_rom.c
index fac0da5a3a..8e2b29d61d 100644
--- a/src/southbridge/nvidia/ck804/ck804_enable_rom.c
+++ b/src/southbridge/nvidia/ck804/ck804_enable_rom.c
@@ -3,10 +3,10 @@
* by yhlu@tyan.com
*/
-#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
-#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE
+#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
+#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
#else
-#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE
+#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
#endif
static void ck804_enable_rom(void)
diff --git a/src/southbridge/nvidia/ck804/ck804_lpc.c b/src/southbridge/nvidia/ck804/ck804_lpc.c
index db7c29ba84..bb2cf99401 100644
--- a/src/southbridge/nvidia/ck804/ck804_lpc.c
+++ b/src/southbridge/nvidia/ck804/ck804_lpc.c
@@ -108,8 +108,8 @@ static void setup_ioapic(unsigned long ioapic_base)
#define SLOW_CPU_OFF 0
#define SLOW_CPU__ON 1
-#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
+#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
#endif
static void lpc_common_init(device_t dev)
@@ -198,7 +198,7 @@ static void lpc_init(device_t dev)
#endif
/* power after power fail */
- on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
get_option(&on, "power_on_after_fail");
byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
byte &= ~0x40;
diff --git a/src/southbridge/nvidia/ck804/id.inc b/src/southbridge/nvidia/ck804/id.inc
index 5c0991871b..d8e26ebde4 100644
--- a/src/southbridge/nvidia/ck804/id.inc
+++ b/src/southbridge/nvidia/ck804/id.inc
@@ -3,12 +3,12 @@
.globl __id_start
__id_start:
vendor:
- .asciz MAINBOARD_VENDOR
+ .asciz CONFIG_MAINBOARD_VENDOR
part:
- .asciz MAINBOARD_PART_NUMBER
+ .asciz CONFIG_MAINBOARD_PART_NUMBER
.long __id_end + 0x80 - vendor /* Reverse offset to the vendor ID */
.long __id_end + 0x80 - part /* Reverse offset to the part number */
-.long PAYLOAD_SIZE + ROM_IMAGE_SIZE /* Size of this ROM image */
+.long CONFIG_PAYLOAD_SIZE + CONFIG_ROM_IMAGE_SIZE /* Size of this ROM image */
.globl __id_end
__id_end:
diff --git a/src/southbridge/nvidia/ck804/id.lds b/src/southbridge/nvidia/ck804/id.lds
index 947a2f0c03..d95b9afcf4 100644
--- a/src/southbridge/nvidia/ck804/id.lds
+++ b/src/southbridge/nvidia/ck804/id.lds
@@ -1,5 +1,5 @@
SECTIONS {
- . = (_ROMBASE + ROM_IMAGE_SIZE - 0x80) - (__id_end - __id_start);
+ . = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x80) - (__id_end - __id_start);
.id (.): {
*(.id)
}
diff --git a/src/southbridge/nvidia/ck804/romstrap.lds b/src/southbridge/nvidia/ck804/romstrap.lds
index 5b69024629..f26299f69f 100644
--- a/src/southbridge/nvidia/ck804/romstrap.lds
+++ b/src/southbridge/nvidia/ck804/romstrap.lds
@@ -1,5 +1,5 @@
SECTIONS {
- . = (_ROMBASE + ROM_IMAGE_SIZE - 0x10) - (__romstrap_end - __romstrap_start);
+ . = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x10) - (__romstrap_end - __romstrap_start);
.romstrap (.): {
*(.romstrap)
}
diff --git a/src/southbridge/nvidia/mcp55/Config.lb b/src/southbridge/nvidia/mcp55/Config.lb
index f84fde780f..492cd3fdf9 100644
--- a/src/southbridge/nvidia/mcp55/Config.lb
+++ b/src/southbridge/nvidia/mcp55/Config.lb
@@ -19,7 +19,7 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-uses HAVE_ACPI_TABLES
+uses CONFIG_HAVE_ACPI_TABLES
config chip.h
driver mcp55.o
@@ -35,6 +35,6 @@ driver mcp55_pci.o
driver mcp55_pcie.o
driver mcp55_ht.o
object mcp55_reset.o
-if HAVE_ACPI_TABLES
+if CONFIG_HAVE_ACPI_TABLES
object mcp55_fadt.o
end
diff --git a/src/southbridge/nvidia/mcp55/id.inc b/src/southbridge/nvidia/mcp55/id.inc
index ad386e7eee..880ae4b766 100644
--- a/src/southbridge/nvidia/mcp55/id.inc
+++ b/src/southbridge/nvidia/mcp55/id.inc
@@ -24,12 +24,12 @@
.globl __id_start
__id_start:
vendor:
- .asciz MAINBOARD_VENDOR
+ .asciz CONFIG_MAINBOARD_VENDOR
part:
- .asciz MAINBOARD_PART_NUMBER
+ .asciz CONFIG_MAINBOARD_PART_NUMBER
.long __id_end + 0x80 - vendor /* Reverse offset to the vendor id */
.long __id_end + 0x80 - part /* Reverse offset to the part number */
-.long PAYLOAD_SIZE + ROM_IMAGE_SIZE /* Size of this romimage */
+.long CONFIG_PAYLOAD_SIZE + CONFIG_ROM_IMAGE_SIZE /* Size of this romimage */
.globl __id_end
__id_end:
diff --git a/src/southbridge/nvidia/mcp55/id.lds b/src/southbridge/nvidia/mcp55/id.lds
index 668600a377..53215beb63 100644
--- a/src/southbridge/nvidia/mcp55/id.lds
+++ b/src/southbridge/nvidia/mcp55/id.lds
@@ -20,7 +20,7 @@
*/
SECTIONS {
- . = (_ROMBASE + ROM_IMAGE_SIZE - 0x80) - (__id_end - __id_start);
+ . = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x80) - (__id_end - __id_start);
.id (.): {
*(.id)
}
diff --git a/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c b/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c
index 4bf0756f66..78e587e063 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c
@@ -21,10 +21,10 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#if HT_CHAIN_END_UNITID_BASE != 0x20
- #define MCP55_DEVN_BASE HT_CHAIN_END_UNITID_BASE
+#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
+ #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
#else
- #define MCP55_DEVN_BASE HT_CHAIN_UNITID_BASE
+ #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
#endif
static void mcp55_enable_rom(void)
diff --git a/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c b/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c
index 4775d9f516..1c7a26bffc 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c
@@ -21,10 +21,10 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#if HT_CHAIN_END_UNITID_BASE != 0x20
- #define MCP55_DEVN_BASE HT_CHAIN_END_UNITID_BASE
+#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
+ #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
#else
- #define MCP55_DEVN_BASE HT_CHAIN_UNITID_BASE
+ #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
#endif
#define EHCI_BAR_INDEX 0x10
diff --git a/src/southbridge/nvidia/mcp55/mcp55_lpc.c b/src/southbridge/nvidia/mcp55/mcp55_lpc.c
index 4aff452958..4faaf08fe9 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_lpc.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_lpc.c
@@ -132,8 +132,8 @@ static void setup_ioapic(unsigned long ioapic_base, int master)
#define SLOW_CPU_OFF 0
#define SLOW_CPU__ON 1
-#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
+#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
#endif
static void lpc_common_init(device_t dev, int master)
@@ -181,7 +181,7 @@ static void lpc_init(device_t dev)
/* power after power fail */
#if 1
- on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
get_option(&on, "power_on_after_fail");
byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
byte &= ~0x40;
diff --git a/src/southbridge/nvidia/mcp55/mcp55_smbus.c b/src/southbridge/nvidia/mcp55/mcp55_smbus.c
index cff22a3af7..484702ae64 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_smbus.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_smbus.c
@@ -94,7 +94,7 @@ static struct smbus_bus_operations lops_smbus_bus = {
.write_byte = lsmbus_write_byte,
};
-#if HAVE_ACPI_TABLES == 1
+#if CONFIG_HAVE_ACPI_TABLES == 1
unsigned pm_base;
#endif
@@ -115,7 +115,7 @@ static void mcp55_sm_read_resources(device_t dev)
static void mcp55_sm_init(device_t dev)
{
-#if HAVE_ACPI_TABLES == 1
+#if CONFIG_HAVE_ACPI_TABLES == 1
struct resource *res;
res = find_resource(dev, 0x60);
diff --git a/src/southbridge/nvidia/mcp55/romstrap.lds b/src/southbridge/nvidia/mcp55/romstrap.lds
index 8a4efd49f1..c45f864152 100644
--- a/src/southbridge/nvidia/mcp55/romstrap.lds
+++ b/src/southbridge/nvidia/mcp55/romstrap.lds
@@ -20,7 +20,7 @@
*/
SECTIONS {
- . = (_ROMBASE + ROM_IMAGE_SIZE - 0x10) - (__romstrap_end - __romstrap_start);
+ . = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x10) - (__romstrap_end - __romstrap_start);
.romstrap (.): {
*(.romstrap)
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-05 06:16:56 +0000