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-rw-r--r--src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c2
-rw-r--r--src/southbridge/nvidia/mcp55/mcp55_fadt.c8
2 files changed, 5 insertions, 5 deletions
diff --git a/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c b/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
index 6d776d38bd..06d9f273c4 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
@@ -388,7 +388,7 @@ static int mcp55_early_setup_x(void)
int mcp55_num = 0;
unsigned busnx;
unsigned devnx;
- int ht_c_index,j;
+ int ht_c_index;
/* FIXME: multi pci segment handling */
diff --git a/src/southbridge/nvidia/mcp55/mcp55_fadt.c b/src/southbridge/nvidia/mcp55/mcp55_fadt.c
index 7c7ad6954c..8d80409719 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_fadt.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_fadt.c
@@ -51,8 +51,8 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
printk(BIOS_INFO, "ACPI: pm_base: %u...\n", pm_base);
- fadt->firmware_ctrl = facs;
- fadt->dsdt = dsdt;
+ fadt->firmware_ctrl = (u32)facs;
+ fadt->dsdt = (u32)dsdt;
fadt->preferred_pm_profile = 1; //check
fadt->sci_int = 9;
/* disable system management mode by setting to 0 */
@@ -108,9 +108,9 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
fadt->reset_reg.addrh = 0x0;
fadt->reset_value = 0;
- fadt->x_firmware_ctl_l = facs;
+ fadt->x_firmware_ctl_l = (u32)facs;
fadt->x_firmware_ctl_h = 0;
- fadt->x_dsdt_l = dsdt;
+ fadt->x_dsdt_l = (u32)dsdt;
fadt->x_dsdt_h = 0;
fadt->x_pm1a_evt_blk.space_id = 1;