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-rw-r--r--src/southbridge/via/vt8237r/vt8237r_early_smbus.c8
-rw-r--r--src/southbridge/via/vt8237r/vt8237r_lpc.c16
2 files changed, 12 insertions, 12 deletions
diff --git a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c b/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
index aa75f50651..9f824437bf 100644
--- a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
+++ b/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
@@ -171,10 +171,10 @@ void enable_smbus(void)
}
/**
- * A fixup for some systems that need time for the SMBus to "warm up". This is
- * needed on some VT823x based systems, where the SMBus spurts out bad data for
- * a short time after power on. This has been seen on the VIA Epia series and
- * Jetway J7F2-series. It reads the ID byte from SMBus, looking for
+ * A fixup for some systems that need time for the SMBus to "warm up". This is
+ * needed on some VT823x based systems, where the SMBus spurts out bad data for
+ * a short time after power on. This has been seen on the VIA Epia series and
+ * Jetway J7F2-series. It reads the ID byte from SMBus, looking for
* known-good data from a slot/address. Exits on either good data or a timeout.
*
* TODO: This should probably go into some global file, but one would need to
diff --git a/src/southbridge/via/vt8237r/vt8237r_lpc.c b/src/southbridge/via/vt8237r/vt8237r_lpc.c
index f7acb75766..5a08e3b16f 100644
--- a/src/southbridge/via/vt8237r/vt8237r_lpc.c
+++ b/src/southbridge/via/vt8237r/vt8237r_lpc.c
@@ -187,7 +187,7 @@ static void setup_pm(device_t dev)
* 6 = SUSST# Deasserted Before PWRGD for STD
* 5 = Keyboard/Mouse Swap
* 4 = PWRGOOD reset on VT8237A/S
- * 3 = GPO26/GPO27 is GPO
+ * 3 = GPO26/GPO27 is GPO
* 2 = Disable Alert on Lan
* 1 = SUSCLK/GPO4
* 0 = USB Wakeup
@@ -247,7 +247,7 @@ static void setup_pm(device_t dev)
static void vt8237r_init(struct device *dev)
{
u8 enables;
-
+
#if CONFIG_EPIA_VT8237R_INIT
printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n");
/*
@@ -260,9 +260,9 @@ static void vt8237r_init(struct device *dev)
enables = pci_read_config8(dev, 0xe5);
enables |= 0x23;
pci_write_config8(dev, 0xe5, enables);
-
- /*
- * Enable Flash Write Access.
+
+ /*
+ * Enable Flash Write Access.
* Note EPIA-N Does not use REQ5 or PCISTP#(Hang)
*/
enables = pci_read_config8(dev, 0xe4);
@@ -274,14 +274,14 @@ static void vt8237r_init(struct device *dev)
enables |= 0x80;
pci_write_config8(dev, 0x4E, enables);
-#else
+#else
printk(BIOS_SPEW, "Entering vt8237r_init.\n");
/*
* Enable SATA LED, disable special CPU Frequency Change -
* GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs.
*/
pci_write_config8(dev, 0xe5, 0x09);
-
+
/* REQ5 as PCI request input - should be together with INTE-INTH. */
pci_write_config8(dev, 0xe4, 0x4);
#endif
@@ -329,7 +329,7 @@ static void vt8237s_init(struct device *dev)
(VT8237S_SPI_MEM_BASE >> 8) | (tmp & 0xFF000000));
/*
- * REQ5 as PCI request input - should be together with INTE-INTH.
+ * REQ5 as PCI request input - should be together with INTE-INTH.
*/
pci_write_config8(dev, 0xe4, 0x04);