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Diffstat (limited to 'src/southbridge/via/vt8237r')
-rw-r--r--src/southbridge/via/vt8237r/early_smbus.c4
-rw-r--r--src/southbridge/via/vt8237r/lpc.c2
2 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/via/vt8237r/early_smbus.c b/src/southbridge/via/vt8237r/early_smbus.c
index b087a471b4..b41e1ad925 100644
--- a/src/southbridge/via/vt8237r/early_smbus.c
+++ b/src/southbridge/via/vt8237r/early_smbus.c
@@ -274,7 +274,7 @@ void vt8237_sb_enable_fid_vid(void)
/* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1);
- /* Enable ACPI accessm RTC signal gated with PSON. */
+ /* Enable ACPI access RTC signal gated with PSON. */
pci_write_config8(dev, 0x81, 0x84);
/* chipset-specific parts */
@@ -342,7 +342,7 @@ static int acpi_is_wakeup_early(void) {
/* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1);
- /* Enable ACPI accessm RTC signal gated with PSON. */
+ /* Enable ACPI access RTC signal gated with PSON. */
pci_write_config8(dev, 0x81, 0x84);
tmp = inw(VT8237R_ACPI_IO_BASE + 0x04);
diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index d8251a08fa..4949de6560 100644
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -215,7 +215,7 @@ static void setup_pm(device_t dev)
/* Disable GP3 timer. */
pci_write_config8(dev, 0x98, 0);
- /* Enable ACPI accessm RTC signal gated with PSON. */
+ /* Enable ACPI access RTC signal gated with PSON. */
pci_write_config8(dev, 0x81, 0x84);
/* Clear status events. */