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-rw-r--r--src/southbridge/via/Makefile.inc4
-rw-r--r--src/southbridge/via/k8t890/Kconfig14
-rw-r--r--src/southbridge/via/k8t890/bridge.c11
-rw-r--r--src/southbridge/via/k8t890/chrome.c14
-rw-r--r--src/southbridge/via/k8t890/ctrl.c48
-rw-r--r--src/southbridge/via/k8t890/dram.c30
-rw-r--r--src/southbridge/via/k8t890/early_car.c15
-rw-r--r--src/southbridge/via/k8t890/error.c21
-rw-r--r--src/southbridge/via/k8t890/host.c23
-rw-r--r--src/southbridge/via/k8t890/host_ctrl.c30
-rw-r--r--src/southbridge/via/k8t890/k8t890.h1
-rw-r--r--src/southbridge/via/k8t890/romstrap.inc22
-rw-r--r--src/southbridge/via/k8t890/traf_ctrl.c3
-rw-r--r--src/southbridge/via/vt8237r/ctrl.c31
-rw-r--r--src/southbridge/via/vt8237r/lpc.c15
-rw-r--r--src/southbridge/via/vt8237r/vt8237r.c4
16 files changed, 244 insertions, 42 deletions
diff --git a/src/southbridge/via/Makefile.inc b/src/southbridge/via/Makefile.inc
index a1fb94eda9..3c0160a7fe 100644
--- a/src/southbridge/via/Makefile.inc
+++ b/src/southbridge/via/Makefile.inc
@@ -1,3 +1,7 @@
+subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD) += k8t890 # lspci lists B188 and 3188
+subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8T800) += k8t890 # lspci lists 0282, 1282, 2282, 3282, and 7282
+subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8T800PRO) += k8t890 # lspci lists 0282, 1282, 2282, 3282, and 7282
+subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8M800) += k8t890
subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8T890) += k8t890
subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8M890) += k8t890
subdirs-$(CONFIG_SOUTHBRIDGE_VIA_VT8231) += vt8231
diff --git a/src/southbridge/via/k8t890/Kconfig b/src/southbridge/via/k8t890/Kconfig
index 3626a05681..94b62b0be2 100644
--- a/src/southbridge/via/k8t890/Kconfig
+++ b/src/southbridge/via/k8t890/Kconfig
@@ -1,3 +1,15 @@
+config SOUTHBRIDGE_VIA_K8M800 #K8M800 not tested
+ bool
+
+config SOUTHBRIDGE_VIA_K8T800_OLD # not tested
+ bool
+
+config SOUTHBRIDGE_VIA_K8T800
+ bool
+
+config SOUTHBRIDGE_VIA_K8T800PRO
+ bool
+
config SOUTHBRIDGE_VIA_K8M890
bool
@@ -40,5 +52,5 @@ config VIDEO_MB
config ID_SECTION_OFFSET
hex
- default 0x80 if SOUTHBRIDGE_VIA_K8M890 || SOUTHBRIDGE_VIA_K8T890
+ default 0x80 if SOUTHBRIDGE_VIA_K8M800 || SOUTHBRIDGE_VIA_K8T800_OLD || SOUTHBRIDGE_VIA_K8T800 || SOUTHBRIDGE_VIA_K8T800PRO || SOUTHBRIDGE_VIA_K8M890 || SOUTHBRIDGE_VIA_K8T890
diff --git a/src/southbridge/via/k8t890/bridge.c b/src/southbridge/via/k8t890/bridge.c
index 3e1e81730d..701b93d5f1 100644
--- a/src/southbridge/via/k8t890/bridge.c
+++ b/src/southbridge/via/k8t890/bridge.c
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
@@ -21,12 +21,13 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <console/console.h>
-#include "k8t890.h"
+#include "k8x8xx.h"
static void bridge_enable(struct device *dev)
{
u8 tmp;
print_debug("B188 device dump\n");
+
/* VIA recommends this, sorry no known info. */
writeback(dev, 0x40, 0x91);
@@ -63,7 +64,11 @@ static const struct device_operations bridge_ops = {
.ops_pci = 0,
};
-static const struct pci_driver northbridge_driver __pci_driver = {
+/*
+ * K8T890 and K8T800 both use device B188 as the bridge, so no need to
+ * add a separate driver
+ */
+static const struct pci_driver northbridge_driver_890 __pci_driver = {
.ops = &bridge_ops,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_K8T890CE_BR,
diff --git a/src/southbridge/via/k8t890/chrome.c b/src/southbridge/via/k8t890/chrome.c
index 5880026552..ad8669ea9c 100644
--- a/src/southbridge/via/k8t890/chrome.c
+++ b/src/southbridge/via/k8t890/chrome.c
@@ -23,7 +23,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <string.h> /* for memset */
-#include "k8t890.h"
+#include "k8x8xx.h"
#if CONFIG_VGA
#include <pc80/vga_io.h>
@@ -167,8 +167,14 @@ chrome_ops = {
.enable = 0,
};
-static const struct pci_driver unichrome_driver __pci_driver = {
+static const struct pci_driver unichrome_driver_800 __pci_driver = {
.ops = &chrome_ops,
- .vendor = 0x1106,
- .device = 0x3230,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8M800_CHROME,
+};
+
+static const struct pci_driver unichrome_driver_890 __pci_driver = {
+ .ops = &chrome_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8M890_CHROME,
};
diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c
index bb3cc02217..a2a5fe9edc 100644
--- a/src/southbridge/via/k8t890/ctrl.c
+++ b/src/southbridge/via/k8t890/ctrl.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -22,6 +23,7 @@
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <console/console.h>
+#include "k8x8xx.h"
/* We support here K8M890/K8T890 and VT8237R PCI1/Vlink which setup is not in separate
* PCI device 0:11.7, but it is mapped to PCI 0:0.7 (0x70-0x7c for PCI1)
@@ -32,20 +34,31 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb)
u8 regm, regm3;
device_t devfun3;
-
+
devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_K8T890CE_3, 0);
+ PCI_DEVICE_ID_VIA_K8T800_DRAM, 0);
+
+ if (!devfun3)
+ devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_K8M800_DRAM, 0);
if (!devfun3)
devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_K8T890CE_3, 0);
+
+ if (!devfun3)
+ devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8T890CF_3, 0);
if (!devfun3)
devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8M890CE_3, 0);
+
+ if(!devfun3)
+ die("\n vt8237r_cfg: Unable to find K8x8xx bridge via PCI scan. Stopping.\n");
pci_write_config8(dev, 0x70, 0xc2);
-
+
/* PCI Control */
pci_write_config8(dev, 0x72, 0xee);
pci_write_config8(dev, 0x73, 0x01);
@@ -87,6 +100,7 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb)
/* Shadow page F + memhole copy */
regm = pci_read_config8(devfun3, 0x83);
pci_write_config8(dev, 0x63, regm3 | (regm & 0x3F));
+
}
@@ -143,8 +157,10 @@ static void vt8237r_vlink_init(struct device *dev)
pci_write_config8(dev, 0x48, 0xa3);
}
-static void ctrl_init(struct device *dev) {
+static void ctrl_init(struct device *dev)
+{
+ print_debug("K8x8xx: Initializing V-Link to VT8237R sb: ");
/* TODO: Fix some ordering issue fo V-link set Rx77[6] and PCI1_Rx4F[0]
should to 1 */
@@ -161,7 +177,13 @@ static void ctrl_init(struct device *dev) {
if (devsb) {
vt8237r_vlink_init(dev);
vt8237r_cfg(dev, devsb);
+ } else {
+ print_debug("VT8237R LPC not found !\n");
+ return;
}
+ print_debug(" Done\n");
+ print_debug(" VIA_X_7 device dump:\n");
+ dump_south(dev);
}
@@ -173,19 +195,31 @@ static const struct device_operations ctrl_ops = {
.ops_pci = 0,
};
-static const struct pci_driver northbridge_driver_t __pci_driver = {
+static const struct pci_driver northbridge_driver_t800 __pci_driver = {
+ .ops = &ctrl_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8T800_NB_SB_CTR,
+};
+
+static const struct pci_driver northbridge_driver_m800 __pci_driver = {
+ .ops = &ctrl_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8M800_NB_SB_CTR,
+};
+
+static const struct pci_driver northbridge_driver_t890 __pci_driver = {
.ops = &ctrl_ops,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_K8T890CE_7,
};
-static const struct pci_driver northbridge_driver_tcf __pci_driver = {
+static const struct pci_driver northbridge_driver_t890cf __pci_driver = {
.ops = &ctrl_ops,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_K8T890CF_7,
};
-static const struct pci_driver northbridge_driver_m __pci_driver = {
+static const struct pci_driver northbridge_driver_m890 __pci_driver = {
.ops = &ctrl_ops,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_K8M890CE_7,
diff --git a/src/southbridge/via/k8t890/dram.c b/src/southbridge/via/k8t890/dram.c
index 6c52fb1d02..dd65b508ca 100644
--- a/src/southbridge/via/k8t890/dram.c
+++ b/src/southbridge/via/k8t890/dram.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -25,7 +26,7 @@
#include <cpu/amd/mtrr.h>
#include <pc80/mc146818rtc.h>
#include <bitops.h>
-#include "k8t890.h"
+#include "k8x8xx.h"
static void dram_enable(struct device *dev)
{
@@ -34,9 +35,9 @@ static void dram_enable(struct device *dev)
/*
* Enable Lowest Interrupt arbitration for APIC, enable NB APIC
- * decoding, MSI support, no SMRAM, compatible SMM.
+ * decoding, MSI support, no SMRAM, compatible SMM.
*/
- pci_write_config8(dev, 0x86, 0x39);
+ pci_write_config8(dev, 0x86, 0x19);
/*
* We want to use the 0xC0000-0xEFFFF as RAM mark area as RW, even if
@@ -64,6 +65,9 @@ static void dram_enable(struct device *dev)
/* The Address Next to the Last Valid DRAM Address */
pci_write_config16(dev, 0x88, (msr.lo >> 24) | reg);
+
+ print_debug(" VIA_X_3 device dump:\n");
+ dump_south(dev);
}
@@ -110,6 +114,8 @@ int
k8m890_host_fb_size_get(void)
{
struct device *dev = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_K8M800_DRAM, 0);
+ if(!dev) dev = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8M890CE_3, 0);
unsigned char tmp;
@@ -164,19 +170,31 @@ static const struct device_operations dram_ops_m = {
.ops_pci = 0,
};
-static const struct pci_driver northbridge_driver_t __pci_driver = {
+static const struct pci_driver northbridge_driver_t800 __pci_driver = {
+ .ops = &dram_ops_t,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8T800_DRAM,
+};
+
+static const struct pci_driver northbridge_driver_m800 __pci_driver = {
+ .ops = &dram_ops_m,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8M800_DRAM,
+};
+
+static const struct pci_driver northbridge_driver_t890 __pci_driver = {
.ops = &dram_ops_t,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_K8T890CE_3,
};
-static const struct pci_driver northbridge_driver_tcf __pci_driver = {
+static const struct pci_driver northbridge_driver_t890cf __pci_driver = {
.ops = &dram_ops_t,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_K8T890CF_3,
};
-static const struct pci_driver northbridge_driver_m __pci_driver = {
+static const struct pci_driver northbridge_driver_m890 __pci_driver = {
.ops = &dram_ops_m,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_K8M890CE_3,
diff --git a/src/southbridge/via/k8t890/early_car.c b/src/southbridge/via/k8t890/early_car.c
index da7bbc69c5..240e5aa75e 100644
--- a/src/southbridge/via/k8t890/early_car.c
+++ b/src/southbridge/via/k8t890/early_car.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -25,7 +26,7 @@
#include <stdlib.h>
#include <cbmem.h>
#include <arch/io.h>
-#include "k8t890.h"
+#include "k8x8xx.h"
/* The 256 bytes of NVRAM for S3 storage, 256B aligned */
#define K8T890_NVRAM_IO_BASE 0xf00
@@ -36,6 +37,8 @@ static u8 ldtreg[3] = {0x86, 0xa6, 0xc6};
/* This functions sets KT890 link frequency and width to same values as
* it has been setup on K8 side, by AMD NB init.
+ * This will not work for K8T800_OLD, which has a slightly different
+ * register arrangement (device 3188)
*/
u8 k8t890_early_setup_ht(void)
@@ -66,7 +69,17 @@ u8 k8t890_early_setup_ht(void)
ldtnr = 2;
}
+#if defined(CONFIG_SOUTHBRIDGE_VIA_K8M800)
+ print_debug("K8M800 found at LDT ");
+#elif defined(CONFIG_SOUTHBRIDGE_VIA_K8T800)
+ print_debug("K8T800 found at LDT ");
+#elif defined(CONFIG_SOUTHBRIDGE_VIA_K8T800PRO)
+ print_debug("K8T800 Pro found at LDT ");
+#elif defined(CONFIG_SOUTHBRIDGE_VIA_K8M890)
+ print_debug("K8M890 found at LDT ");
+#elif defined(CONFIG_SOUTHBRIDGE_VIA_K8T890)
print_debug("K8T890 found at LDT ");
+#endif
print_debug_hex8(ldtnr);
/* get the maximum widths for both sides */
diff --git a/src/southbridge/via/k8t890/error.c b/src/southbridge/via/k8t890/error.c
index a9b10d56bc..a5f86bf4e9 100644
--- a/src/southbridge/via/k8t890/error.c
+++ b/src/southbridge/via/k8t890/error.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -21,9 +22,11 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <console/console.h>
+#include "k8x8xx.h"
static void error_enable(struct device *dev)
{
+ print_debug(" K8x8xx: Enabling NB error reporting: ");
/*
* bit0 - Enable V-link parity error reporting in 0x50 bit0 (RWC)
* bit6 - Parity Error/SERR# Report Through V-Link to SB
@@ -31,7 +34,11 @@ static void error_enable(struct device *dev)
*/
pci_write_config8(dev, 0x58, 0x81);
+ print_debug("Done\n");
/* TODO: enable AGP errors reporting on K8M890 */
+
+ print_debug(" VIA_X_1 device dump:\n");
+ dump_south(dev);
}
static const struct device_operations error_ops = {
@@ -42,7 +49,19 @@ static const struct device_operations error_ops = {
.ops_pci = 0,
};
-static const struct pci_driver northbridge_driver_t __pci_driver = {
+static const struct pci_driver northbridge_driver_t800 __pci_driver = {
+ .ops = &error_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8T800_ERR,
+};
+
+static const struct pci_driver northbridge_driver_m800 __pci_driver = {
+ .ops = &error_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8M800_ERR,
+};
+
+static const struct pci_driver northbridge_driver_t890 __pci_driver = {
.ops = &error_ops,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_K8T890CE_1,
diff --git a/src/southbridge/via/k8t890/host.c b/src/southbridge/via/k8t890/host.c
index 9a0118c778..13bd69330f 100644
--- a/src/southbridge/via/k8t890/host.c
+++ b/src/southbridge/via/k8t890/host.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -22,13 +23,15 @@
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <console/console.h>
-#include "k8t890.h"
+#include "k8x8xx.h"
static void host_enable(struct device *dev)
{
/* Multiple function control */
pci_write_config8(dev, K8T890_MULTIPLE_FN_EN, 0x01);
+ print_debug(" VIA_X_0 device dump:\n");
+ dump_south(dev);
}
@@ -70,19 +73,31 @@ static const struct device_operations host_ops_m = {
.ops_pci = 0,
};
-static const struct pci_driver northbridge_driver_t __pci_driver = {
+static const struct pci_driver northbridge_driver_t800 __pci_driver = {
+ .ops = &host_ops_t,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8T800_HT_AGP_CTR,
+};
+
+static const struct pci_driver northbridge_driver_m800 __pci_driver = {
+ .ops = &host_ops_m,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8M800_HT_AGP_CTR,
+};
+
+static const struct pci_driver northbridge_driver_t890 __pci_driver = {
.ops = &host_ops_t,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_K8T890CE_0,
};
-static const struct pci_driver northbridge_driver_tcf __pci_driver = {
+static const struct pci_driver northbridge_driver_t890cf __pci_driver = {
.ops = &host_ops_t,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_K8T890CF_0,
};
-static const struct pci_driver northbridge_driver_m __pci_driver = {
+static const struct pci_driver northbridge_driver_m890 __pci_driver = {
.ops = &host_ops_m,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_K8M890CE_0,
diff --git a/src/southbridge/via/k8t890/host_ctrl.c b/src/southbridge/via/k8t890/host_ctrl.c
index 43d01ee369..5d46a00c96 100644
--- a/src/southbridge/via/k8t890/host_ctrl.c
+++ b/src/southbridge/via/k8t890/host_ctrl.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -24,15 +25,13 @@
#include <console/console.h>
#include <cbmem.h>
#include <arch/io.h>
-#include "k8t890.h"
+#include "k8x8xx.h"
/* this may be later merged */
/* This fine tunes the HT link settings, which were loaded by ROM strap. */
-static void host_ctrl_enable_k8t890(struct device *dev)
+static void host_ctrl_enable_k8t8xx(struct device *dev)
{
- dump_south(dev);
-
/*
* Bit 4 is reserved but set by AW. Set PCI to HT outstanding
* requests to 3.
@@ -85,11 +84,12 @@ static void host_ctrl_enable_k8t890(struct device *dev)
writeback(dev, 0xc4, 0x50);
writeback(dev, 0xc5, 0x50);
+ print_debug(" VIA_X_2 device dump:\n");
dump_south(dev);
}
/* This fine tunes the HT link settings, which were loaded by ROM strap. */
-static void host_ctrl_enable_k8m890(struct device *dev) {
+static void host_ctrl_enable_k8m8xx(struct device *dev) {
/*
* Set PCI to HT outstanding requests to 03.
@@ -126,7 +126,7 @@ static const struct device_operations host_ctrl_ops_t = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
- .enable = host_ctrl_enable_k8t890,
+ .enable = host_ctrl_enable_k8t8xx,
.ops_pci = 0,
};
@@ -134,17 +134,29 @@ static const struct device_operations host_ctrl_ops_m = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
- .enable = host_ctrl_enable_k8m890,
+ .enable = host_ctrl_enable_k8m8xx,
.ops_pci = 0,
};
-static const struct pci_driver northbridge_driver_t __pci_driver = {
+static const struct pci_driver northbridge_driver_t800 __pci_driver = {
+ .ops = &host_ctrl_ops_t,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8T800_HOST_CTR,
+};
+
+static const struct pci_driver northbridge_driver_m800 __pci_driver = {
+ .ops = &host_ctrl_ops_m,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_K8M800_HOST_CTR,
+};
+
+static const struct pci_driver northbridge_driver_t890 __pci_driver = {
.ops = &host_ctrl_ops_t,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_K8T890CE_2,
};
-static const struct pci_driver northbridge_driver_m __pci_driver = {
+static const struct pci_driver northbridge_driver_m890 __pci_driver = {
.ops = &host_ctrl_ops_m,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_K8M890CE_2,
diff --git a/src/southbridge/via/k8t890/k8t890.h b/src/southbridge/via/k8t890/k8t890.h
index faa6a81d3d..fd450ef9da 100644
--- a/src/southbridge/via/k8t890/k8t890.h
+++ b/src/southbridge/via/k8t890/k8t890.h
@@ -41,6 +41,7 @@
#ifdef __PRE_RAM__
u8 k8t890_early_setup_ht(void);
+#define k8x8xx_early_setup_ht() k8t890_early_setup_ht()
#else
#include <device/device.h>
#if 0
diff --git a/src/southbridge/via/k8t890/romstrap.inc b/src/southbridge/via/k8t890/romstrap.inc
index aaaa76694d..4add0087e7 100644
--- a/src/southbridge/via/k8t890/romstrap.inc
+++ b/src/southbridge/via/k8t890/romstrap.inc
@@ -33,6 +33,27 @@ __romstrap_start:
* Below are some Dev0 Func2 HT control registers values,
* depending on strap pin, one of below lines is used.
*/
+#if CONFIG_SOUTHBRIDGE_VIA_K8M800 || CONFIG_SOUTHBRIDGE_VIA_K8T800
+
+tblpointer:
+.long 0x50220000, 0X619707C2
+.long 0x50220000, 0X619707C2
+.long 0x50220000, 0X619707C2
+.long 0x0
+.long 0x0
+.long 0x0
+.long 0x0
+.long 0x0
+.long 0x0
+.long 0x0
+.long 0x0
+.long 0x0
+.long 0x0
+.long 0x0
+.long 0x0
+
+#elif CONFIG_SOUTHBRIDGE_VIA_K8M890 || CONFIG_SOUTHBRIDGE_VIA_K8T890
+
tblpointer:
.long 0x504400AA, 0x61970FC2 //;200M
.long 0x504400AA, 0x61970FC2 //;400M
@@ -50,6 +71,7 @@ tblpointer:
.long 0x0
.long 0x0
+#endif
/*
* The pointer to above table should be at 0xffffd,
* the table itself MUST be aligned to 128B it seems!
diff --git a/src/southbridge/via/k8t890/traf_ctrl.c b/src/southbridge/via/k8t890/traf_ctrl.c
index 55b3a13ac7..d3ed1e7fb0 100644
--- a/src/southbridge/via/k8t890/traf_ctrl.c
+++ b/src/southbridge/via/k8t890/traf_ctrl.c
@@ -138,6 +138,9 @@ static const struct device_operations traf_ctrl_ops_t = {
.ops_pci = 0,
};
+/* K8X800 chipsets have no APIC; no 800 PCI ids here */
+
+
static const struct pci_driver northbridge_driver_t __pci_driver = {
.ops = &traf_ctrl_ops_t,
.vendor = PCI_VENDOR_ID_VIA,
diff --git a/src/southbridge/via/vt8237r/ctrl.c b/src/southbridge/via/vt8237r/ctrl.c
index f3cc30ed88..b268ad54e9 100644
--- a/src/southbridge/via/vt8237r/ctrl.c
+++ b/src/southbridge/via/vt8237r/ctrl.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -32,7 +33,13 @@ static void vt8237_cfg(struct device *dev)
device_t devfun3;
devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_K8T890CE_3, 0);
+ PCI_DEVICE_ID_VIA_K8T800_DRAM, 0);
+ if (!devfun3)
+ devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_K8M800_DRAM, 0);
+ if (!devfun3)
+ devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_K8T890CE_3, 0);
if (!devfun3)
devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8M890CE_3, 0);
@@ -108,7 +115,13 @@ static void vt8237s_vlink_init(struct device *dev)
device_t devfun7;
devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_K8T890CE_7, 0);
+ PCI_DEVICE_ID_VIA_K8T800_NB_SB_CTR, 0);
+ if (!devfun7)
+ devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_K8M800_NB_SB_CTR, 0);
+ if (!devfun7)
+ devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_K8T890CE_7, 0);
if (!devfun7)
devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8M890CE_7, 0);
@@ -117,7 +130,10 @@ static void vt8237s_vlink_init(struct device *dev)
PCI_DEVICE_ID_VIA_K8T890CF_7, 0);
/* No pairing NB was found. */
if (!devfun7)
+ {
+ print_debug("vt8237s_vlink_init: No pairing NB was found.\n");
return;
+ }
/*
* This init code is valid only for the VT8237S! For different
@@ -174,7 +190,13 @@ static void vt8237a_vlink_init(struct device *dev)
device_t devfun7;
devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_K8T890CE_7, 0);
+ PCI_DEVICE_ID_VIA_K8T800_NB_SB_CTR, 0);
+ if (!devfun7)
+ devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_K8M800_NB_SB_CTR, 0);
+ if (!devfun7)
+ devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_K8T890CE_7, 0);
if (!devfun7)
devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8M890CE_7, 0);
@@ -183,7 +205,10 @@ static void vt8237a_vlink_init(struct device *dev)
PCI_DEVICE_ID_VIA_K8T890CF_7, 0);
/* No pairing NB was found. */
if (!devfun7)
+ {
+ print_debug("vt8237a_vlink_init: No pairing NB was found.\n");
return;
+ }
/*
* This init code is valid only for the VT8237A! For different
diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index 3ffc377572..61f4989f54 100644
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -299,11 +299,20 @@ static void vt8237r_init(struct device *dev)
*/
pci_write_config8(dev, 0x48, 0x0c);
#else
+
+ #if CONFIG_SOUTHBRIDGE_VIA_K8T800
+ /* It seems that when we pair with the K8T800, we need to disable
+ * the A2 mask
+ */
+ pci_write_config8(dev, 0x48, 0x0c);
+ #else
/*
* Set Read Pass Write Control Enable
* (force A2 from APIC FSB to low).
*/
pci_write_config8(dev, 0x48, 0x8c);
+ #endif
+
#endif
southbridge_init_common(dev);
@@ -319,6 +328,8 @@ static void vt8237r_init(struct device *dev)
#endif
printk(BIOS_SPEW, "Leaving %s.\n", __func__);
+ printk(BIOS_SPEW, "And taking a dump:\n");
+ dump_south(dev);
}
static void vt8237a_init(struct device *dev)
@@ -469,6 +480,7 @@ static void vt8237_common_init(struct device *dev)
* Bit | Meaning
* -------------
* 3 | Bypass APIC De-Assert Message (1=Enable)
+ * 2 | APIC HyperTransport Mode (1=Enable)
* 1 | possibly "INTE#, INTF#, INTG#, INTH# as PCI"
* | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch
* 0 | Dynamic Clock Gating Main Switch (1=Enable)
@@ -485,12 +497,13 @@ static void vt8237_common_init(struct device *dev)
pci_write_config8(dev, 0x4c, 0x44);
/* ROM memory cycles go to LPC. */
- pci_write_config8(dev, 0x59, 0x80);
+ pci_write_config8(dev, 0x59, 0x80);
/*
* Bit | Meaning
* -------------
* 3 | Bypass APIC De-Assert Message (1=Enable)
+ * 2 | APIC HyperTransport Mode (1=Enable)
* 1 | possibly "INTE#, INTF#, INTG#, INTH# as PCI"
* | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch
* 0 | Dynamic Clock Gating Main Switch (1=Enable)
diff --git a/src/southbridge/via/vt8237r/vt8237r.c b/src/southbridge/via/vt8237r/vt8237r.c
index be24bb5dc2..5ba3815145 100644
--- a/src/southbridge/via/vt8237r/vt8237r.c
+++ b/src/southbridge/via/vt8237r/vt8237r.c
@@ -40,9 +40,9 @@ void writeback(struct device *dev, u16 where, u8 what)
if (regval != what) {
print_debug("Writeback to ");
print_debug_hex8(where);
- print_debug("failed ");
+ print_debug(" failed ");
print_debug_hex8(regval);
- print_debug("\n "); /* TODO: Drop the space? */
+ print_debug("\n");
}
}
#else
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 22:32:43 +0000