diff options
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/amd/cs5536/Kconfig | 27 | ||||
| -rw-r--r-- | src/southbridge/amd/cs5536/Makefile.inc | 27 | ||||
| -rw-r--r-- | src/southbridge/amd/cs5536/chip.h | 39 | ||||
| -rw-r--r-- | src/southbridge/amd/cs5536/cs5536.c | 714 | ||||
| -rw-r--r-- | src/southbridge/amd/cs5536/cs5536.h | 454 | ||||
| -rw-r--r-- | src/southbridge/amd/cs5536/early_setup.c | 276 | ||||
| -rw-r--r-- | src/southbridge/amd/cs5536/early_smbus.c | 39 | ||||
| -rw-r--r-- | src/southbridge/amd/cs5536/ide.c | 57 | ||||
| -rw-r--r-- | src/southbridge/amd/cs5536/pirq.c | 34 | ||||
| -rw-r--r-- | src/southbridge/amd/cs5536/smbus.c | 187 | ||||
| -rw-r--r-- | src/southbridge/amd/cs5536/smbus.h | 32 |
11 files changed, 0 insertions, 1886 deletions
diff --git a/src/southbridge/amd/cs5536/Kconfig b/src/southbridge/amd/cs5536/Kconfig deleted file mode 100644 index 6b06c33642..0000000000 --- a/src/southbridge/amd/cs5536/Kconfig +++ /dev/null @@ -1,27 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008-2009 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SOUTHBRIDGE_AMD_CS5536 - bool - select UDELAY_TSC - -if SOUTHBRIDGE_AMD_CS5536 - -config NO_EARLY_SMBUS - def_bool n - help - Skip the CS5536 early SMBUS initialization. - -endif diff --git a/src/southbridge/amd/cs5536/Makefile.inc b/src/southbridge/amd/cs5536/Makefile.inc deleted file mode 100644 index 4bd88ac587..0000000000 --- a/src/southbridge/amd/cs5536/Makefile.inc +++ /dev/null @@ -1,27 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License version 2 as -## published by the Free Software Foundation. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5536),y) - -romstage-y += early_smbus.c -romstage-y += early_setup.c - -ramstage-y += cs5536.c -ramstage-y += ide.c -ramstage-y += pirq.c -ramstage-y += smbus.c -romstage-y += smbus.c - -endif diff --git a/src/southbridge/amd/cs5536/chip.h b/src/southbridge/amd/cs5536/chip.h deleted file mode 100644 index f5411c04f2..0000000000 --- a/src/southbridge/amd/cs5536/chip.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOUTHBRIDGE_AMD_CS5536 -#define _SOUTHBRIDGE_AMD_CS5536 - -#define MAX_UNWANTED_VPCI 8 /* increase if needed */ - -struct southbridge_amd_cs5536_config { - unsigned int lpc_serirq_enable; /* interrupt enables for LPC bus; each bit is an irq 0-15 */ - unsigned int lpc_serirq_polarity; /* LPC IRQ polarity; each bit is an irq 0-15 */ - unsigned char lpc_serirq_mode; /* 0:Continuous 1:Quiet */ - unsigned int enable_gpio_int_route; /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. See virtual pci spec... */ - unsigned char enable_ide_nand_flash; /* 0:IDE 1:FLASH, if you are using nand flash instead of IDE drive */ - unsigned char enable_USBP4_device; /* Enable USB Port 4 0:host 1:device */ - unsigned int enable_USBP4_overcurrent; /* 0:off, xxxx:overcurrent setting, e.g. 0x3FEA CS5536 - Data Book (pages 380-381) */ - unsigned char com1_enable; /* enable COM1 */ - unsigned int com1_address; /* e.g. 0x3F8 */ - unsigned int com1_irq; /* e.g. 4 */ - unsigned char com2_enable; /* enable COM2 */ - unsigned int com2_address; /* e.g. 0x2F8 */ - unsigned int com2_irq; /* e.g. 3 */ - unsigned int unwanted_vpci[MAX_UNWANTED_VPCI]; /* the following allow you to disable unwanted virtualized PCI devices */ -}; - -#endif /* _SOUTHBRIDGE_AMD_CS5536 */ diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c deleted file mode 100644 index 956994d623..0000000000 --- a/src/southbridge/amd/cs5536/cs5536.c +++ /dev/null @@ -1,714 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <arch/ioapic.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <device/pci_ids.h> -#include <device/smbus.h> -#include <console/console.h> -#include <stdint.h> -#include <pc80/isa-dma.h> -#include <pc80/mc146818rtc.h> -#include <pc80/i8259.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/vr.h> -#include <stdlib.h> -#include "chip.h" -#include "cs5536.h" -#include "smbus.h" - -struct msrinit { - u32 msrnum; - msr_t msr; -}; - -/* Master Configuration Register for Bus Masters.*/ -static struct msrinit SB_MASTER_CONF_TABLE[] = { - {USB2_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000}}, - {ATA_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00048f000}}, - {AC97_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000}}, - {MDD_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00000f000}}, - {0, {0, 0}} -}; - -/* 5536 Clock Gating*/ -static struct msrinit CS5536_CLOCK_GATING_TABLE[] = { - /* MSR Setting*/ - {GLIU_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000004}}, - {GLPCI_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000005}}, - {GLCP_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000004}}, - {MDD_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x050554111}}, /* SMBus clock gating errata (PBZ 2226 & SiBZ 3977) */ - {ATA_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000005}}, - {AC97_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000005}}, - {0, {0, 0}} -}; - -struct acpiinit { - u16 ioreg; - u32 regdata; -}; - -static struct acpiinit acpi_init_table[] = { - {ACPI_IO_BASE + 0x00, 0x01000000}, - {ACPI_IO_BASE + 0x08, 0}, - {ACPI_IO_BASE + 0x0C, 0}, - {ACPI_IO_BASE + 0x1C, 0}, - {ACPI_IO_BASE + 0x18, 0x0FFFFFFFF}, - {ACPI_IO_BASE + 0x00, 0x0000FFFF}, - {PMS_IO_BASE + PM_SCLK, 0x000000E00}, - {PMS_IO_BASE + PM_SED, 0x000004601}, - {PMS_IO_BASE + PM_SIDD, 0x000008C02}, - {PMS_IO_BASE + PM_WKD, 0x0000000A0}, - {PMS_IO_BASE + PM_WKXD, 0x0000000A0}, - {0, 0} -}; - -struct FLASH_DEVICE { - unsigned char fType; /* Flash type: NOR or NAND */ - unsigned char fInterface; /* Flash interface: I/O or Memory */ - unsigned long fMask; /* Flash size/mask */ -}; - -static struct FLASH_DEVICE FlashInitTable[] = { - {FLASH_TYPE_NAND, FLASH_IF_MEM, FLASH_MEM_4K}, /* CS0, or Flash Device 0 */ - {FLASH_TYPE_NONE, 0, 0}, /* CS1, or Flash Device 1 */ - {FLASH_TYPE_NONE, 0, 0}, /* CS2, or Flash Device 2 */ - {FLASH_TYPE_NONE, 0, 0}, /* CS3, or Flash Device 3 */ -}; - -#define FlashInitTableLen (ARRAY_SIZE(FlashInitTable)) - -static u32 FlashPort[] = { - MDD_LBAR_FLSH0, - MDD_LBAR_FLSH1, - MDD_LBAR_FLSH2, - MDD_LBAR_FLSH3 -}; - -/* ***************************************************************************/ -/* **/ -/* * pmChipsetInit*/ -/* **/ -/* * Program ACPI LBAR and initialize ACPI registers.*/ -/* **/ -/* ***************************************************************************/ -static void pmChipsetInit(void) -{ - u32 val = 0; - u16 port; - - port = (PMS_IO_BASE + 0x010); - val = 0x0E00; /* 1ms */ - outl(val, port); - - /* PM_WKXD */ - /* Make sure bits[3:0]=0000b to clear the */ - /* saved Sx state */ - port = (PMS_IO_BASE + 0x034); - val = 0x0A0; /* 5ms */ - outl(val, port); - - /* PM_WKD */ - port = (PMS_IO_BASE + 0x030); - outl(val, port); - - /* PM_SED */ - port = (PMS_IO_BASE + 0x014); - val = 0x04601; /* 5ms, # of 3.57954MHz clock edges */ - outl(val, port); - - /* PM_SIDD */ - port = (PMS_IO_BASE + 0x020); - val = 0x08C02; /* 10ms, # of 3.57954MHz clock edges */ - outl(val, port); -} - -/*************************************************************************** - * - * ChipsetFlashSetup - * - * Flash LBARs need to be setup before VSA init so the PCI BARs have - * correct size info. Call this routine only if flash needs to be - * configured (don't call it if you want IDE). - * - **************************************************************************/ -static void ChipsetFlashSetup(void) -{ - msr_t msr; - int i; - int numEnabled = 0; - - printk(BIOS_DEBUG, "ChipsetFlashSetup: Start\n"); - for (i = 0; i < FlashInitTableLen; i++) { - if (FlashInitTable[i].fType != FLASH_TYPE_NONE) { - printk(BIOS_DEBUG, "Enable CS%d\n", i); - /* we need to configure the memory/IO mask */ - msr = rdmsr(FlashPort[i]); - msr.hi = 0; /* start with the "enabled" bit clear */ - if (FlashInitTable[i].fType == FLASH_TYPE_NAND) - msr.hi |= 0x00000002; - else - msr.hi &= ~0x00000002; - if (FlashInitTable[i].fInterface == FLASH_IF_MEM) - msr.hi |= 0x00000004; - else - msr.hi &= ~0x00000004; - msr.hi |= FlashInitTable[i].fMask; - printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n", FlashPort[i], - msr.hi, msr.lo); - wrmsr(FlashPort[i], msr); - - /* now write-enable the device */ - msr = rdmsr(MDD_NORF_CNTRL); - msr.lo |= (1 << i); - printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL, - msr.hi, msr.lo); - wrmsr(MDD_NORF_CNTRL, msr); - - /* update the number enabled */ - numEnabled++; - } - } - - printk(BIOS_DEBUG, "ChipsetFlashSetup: Finish\n"); - -} - -/* ***************************************************************************/ -/* **/ -/* * enable_ide_nand_flash_header */ -/* Run after VSA init to enable the flash PCI device header */ -/* **/ -/* ***************************************************************************/ -static void enable_ide_nand_flash_header(void) -{ - /* Tell VSA to use FLASH PCI header. Not IDE header. */ - outl(0x80007A40, 0xCF8); - outl(0xDEADBEEF, 0xCFC); -} - -#define RTC_CENTURY 0x32 -#define RTC_DOMA 0x3D -#define RTC_MONA 0x3E - -static void lpc_init(struct southbridge_amd_cs5536_config *sb) -{ - msr_t msr; - - if (sb->lpc_serirq_enable) { - msr.lo = sb->lpc_serirq_enable; - msr.hi = 0; - wrmsr(MDD_IRQM_LPC, msr); - if (sb->lpc_serirq_polarity) { - msr.lo = sb->lpc_serirq_polarity << 16; - msr.lo |= (sb->lpc_serirq_mode << 6) | (1 << 7); /* enable */ - msr.hi = 0; - wrmsr(MDD_LPC_SIRQ, msr); - } - } - - /* Allow DMA from LPC */ - msr = rdmsr(MDD_DMA_MAP); - msr.lo = 0x7777; - wrmsr(MDD_DMA_MAP, msr); - - /* enable the RTC/CMOS century byte at address 32h */ - msr = rdmsr(MDD_RTC_CENTURY_OFFSET); - msr.lo = RTC_CENTURY; - wrmsr(MDD_RTC_CENTURY_OFFSET, msr); - - /* enable the RTC/CMOS day of month and month alarms */ - msr = rdmsr(MDD_RTC_DOMA_IND); - msr.lo = RTC_DOMA; - wrmsr(MDD_RTC_DOMA_IND, msr); - - msr = rdmsr(MDD_RTC_MONA_IND); - msr.lo = RTC_MONA; - wrmsr(MDD_RTC_MONA_IND, msr); - - cmos_init(0); - - isa_dma_init(); -} - - -/** - * Depending on settings in the config struct, enable COM1 or COM2 or both. - * - * If the enable is NOT set, the UARTs are explicitly disabled, which is - * required if (e.g.) there is a Super I/O attached that does COM1 or COM2. - * - * @param sb Southbridge config structure. - */ -static void uarts_init(struct southbridge_amd_cs5536_config *sb) -{ - msr_t msr; - u16 addr = 0; - u32 gpio_addr; - struct device *dev; - - dev = dev_find_device(PCI_VENDOR_ID_AMD, - PCI_DEVICE_ID_AMD_CS5536_ISA, 0); - gpio_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1); - gpio_addr &= ~1; /* Clear I/O bit */ - printk(BIOS_DEBUG, "GPIO_ADDR: %08X\n", gpio_addr); - - /* This could be extended to support IR modes. */ - - /* COM1 */ - if (sb->com1_enable) { - printk(BIOS_SPEW, "uarts_init: enable COM1\n"); - /* Set the address. */ - switch (sb->com1_address) { - case 0x3F8: - addr = 7; - break; - case 0x3E8: - addr = 6; - break; - case 0x2F8: - addr = 5; - break; - case 0x2E8: - addr = 4; - break; - } - msr = rdmsr(MDD_LEG_IO); - msr.lo |= addr << 16; - wrmsr(MDD_LEG_IO, msr); - - /* Set the IRQ. */ - msr = rdmsr(MDD_IRQM_YHIGH); - msr.lo |= sb->com1_irq << 24; - wrmsr(MDD_IRQM_YHIGH, msr); - - /* GPIO8 - UART1_TX */ - /* Set: Output Enable (0x4) */ - outl(GPIOL_8_SET, gpio_addr + GPIOL_OUTPUT_ENABLE); - /* Set: OUTAUX1 Select (0x10) */ - outl(GPIOL_8_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT); - - /* GPIO9 - UART1_RX */ - /* Set: Input Enable (0x20) */ - outl(GPIOL_9_SET, gpio_addr + GPIOL_INPUT_ENABLE); - /* Set: INAUX1 Select (0x34) */ - outl(GPIOL_9_SET, gpio_addr + GPIOL_IN_AUX1_SELECT); - - /* Set: GPIO 8 + 9 Pull Up (0x18) */ - outl(GPIOL_8_SET | GPIOL_9_SET, - gpio_addr + GPIOL_PULLUP_ENABLE); - - /* Enable COM1. - * - * Bit 1 = device enable - * Bit 4 = allow access to the upper banks - */ - msr.lo = (1 << 4) | (1 << 1); - msr.hi = 0; - wrmsr(MDD_UART1_CONF, msr); - } else { - /* Reset and disable COM1. */ - printk(BIOS_SPEW, "uarts_init: disable COM1\n"); - msr = rdmsr(MDD_UART1_CONF); - msr.lo = 1; /* Reset */ - wrmsr(MDD_UART1_CONF, msr); - msr.lo = 0; /* Disabled */ - wrmsr(MDD_UART1_CONF, msr); - - /* Disable the IRQ. */ - msr = rdmsr(MDD_LEG_IO); - msr.lo &= ~(0xF << 16); - wrmsr(MDD_LEG_IO, msr); - } - - /* COM2 */ - if (sb->com2_enable) { - printk(BIOS_SPEW, "uarts_init: enable COM2\n"); - switch (sb->com2_address) { - case 0x3F8: - addr = 7; - break; - case 0x3E8: - addr = 6; - break; - case 0x2F8: - addr = 5; - break; - case 0x2E8: - addr = 4; - break; - } - msr = rdmsr(MDD_LEG_IO); - msr.lo |= addr << 20; - wrmsr(MDD_LEG_IO, msr); - printk(BIOS_SPEW, "uarts_init: wrote COM2 address 0x%x\n", sb->com2_address); - - /* Set the IRQ. */ - msr = rdmsr(MDD_IRQM_YHIGH); - msr.lo |= sb->com2_irq << 28; - wrmsr(MDD_IRQM_YHIGH, msr); - printk(BIOS_SPEW, "uarts_init: set COM2 irq\n"); - - /* GPIO3 - UART2_RX */ - /* Set: Input Enable (0x20) */ - outl(GPIOL_3_SET, gpio_addr + GPIOL_INPUT_ENABLE); - /* Set: INAUX1 Select (0x34) */ - outl(GPIOL_3_SET, gpio_addr + GPIOL_IN_AUX1_SELECT); - - /* GPIO4 - UART2_TX */ - /* Set: Output Enable (0x4) */ - outl(GPIOL_4_SET, gpio_addr + GPIOL_OUTPUT_ENABLE); - printk(BIOS_SPEW, "uarts_init: set output enable\n"); - /* Set: OUTAUX1 Select (0x10) */ - outl(GPIOL_4_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT); - printk(BIOS_SPEW, "uarts_init: set OUTAUX1\n"); - - /* Set: GPIO 3 + 4 Pull Up (0x18) */ - outl(GPIOL_3_SET | GPIOL_4_SET, - gpio_addr + GPIOL_PULLUP_ENABLE); - printk(BIOS_SPEW, "uarts_init: set pullup COM2\n"); - - /* Enable COM2. - * - * Bit 1 = device enable - * Bit 4 = allow access to the upper banks - */ - msr.lo = (1 << 4) | (1 << 1); - msr.hi = 0; - wrmsr(MDD_UART2_CONF, msr); - printk(BIOS_SPEW, "uarts_init: COM2 enabled\n"); - } else { - printk(BIOS_SPEW, "uarts_init: disable COM2\n"); - /* Reset and disable COM2. */ - msr = rdmsr(MDD_UART2_CONF); - msr.lo = 1; /* Reset */ - wrmsr(MDD_UART2_CONF, msr); - msr.lo = 0; /* Disabled */ - wrmsr(MDD_UART2_CONF, msr); - - /* Disable the IRQ. */ - msr = rdmsr(MDD_LEG_IO); - msr.lo &= ~(0xF << 20); - wrmsr(MDD_LEG_IO, msr); - } -} - - -#define HCCPARAMS 0x08 -#define IPREG04 0xA0 - #define USB_HCCPW_SET (1 << 1) -#define UOCCAP 0x00 - #define APU_SET (1 << 15) -#define UOCMUX 0x04 -#define PMUX_HOST 0x02 -#define PMUX_DEVICE 0x03 - #define PUEN_SET (1 << 2) -#define UDCDEVCTL 0x404 - #define UDC_SD_SET (1 << 10) -#define UOCCTL 0x0C - #define PADEN_SET (1 << 7) - -static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) -{ - void *bar; - msr_t msr; - struct device *dev; - - dev = dev_find_device(PCI_VENDOR_ID_AMD, - PCI_DEVICE_ID_AMD_CS5536_EHCI, 0); - if (dev) { - - /* Serial Short Detect Enable */ - msr = rdmsr(USB2_SB_GLD_MSR_CONF); - msr.hi |= USB2_UPPER_SSDEN_SET; - wrmsr(USB2_SB_GLD_MSR_CONF, msr); - - /* write to clear diag register */ - wrmsr(USB2_SB_GLD_MSR_DIAG, rdmsr(USB2_SB_GLD_MSR_DIAG)); - - bar = (void *)pci_read_config32(dev, PCI_BASE_ADDRESS_0); - - /* Make HCCPARAMS writable */ - write32(bar + IPREG04, read32(bar + IPREG04) | USB_HCCPW_SET); - - /* ; EECP=50h, IST=01h, ASPC=1 */ - write32(bar + HCCPARAMS, 0x00005012); - } - - dev = dev_find_device(PCI_VENDOR_ID_AMD, - PCI_DEVICE_ID_AMD_CS5536_OTG, 0); - if (dev) { - bar = (void *)pci_read_config32(dev, PCI_BASE_ADDRESS_0); - - write32(bar + UOCMUX, read32(bar + UOCMUX) & PUEN_SET); - - /* Host or Device? */ - if (sb->enable_USBP4_device) { - write32(bar + UOCMUX, read32(bar + UOCMUX) | PMUX_DEVICE); - } else { - write32(bar + UOCMUX, read32(bar + UOCMUX) | PMUX_HOST); - } - - /* Overcurrent configuration */ - if (sb->enable_USBP4_overcurrent) { - write32(bar + UOCCAP, read32(bar + UOCCAP) - | sb->enable_USBP4_overcurrent); - } - } - - /* PBz#6466: If the UOC(OTG) device, port 4, is configured as a device, - * then perform the following sequence: - * - * - set SD bit in DEVCTRL udc register - * - set PADEN (former OTGPADEN) bit in uoc register - * - set APU bit in uoc register */ - if (sb->enable_USBP4_device) { - dev = dev_find_device(PCI_VENDOR_ID_AMD, - PCI_DEVICE_ID_AMD_CS5536_UDC, 0); - if (dev) { - bar = (void *)pci_read_config32(dev, - PCI_BASE_ADDRESS_0); - write32(bar + UDCDEVCTL, - read32(bar + UDCDEVCTL) | UDC_SD_SET); - - } - - dev = dev_find_device(PCI_VENDOR_ID_AMD, - PCI_DEVICE_ID_AMD_CS5536_OTG, 0); - if (dev) { - bar = (void *)pci_read_config32(dev, - PCI_BASE_ADDRESS_0); - write32(bar + UOCCTL, read32(bar + UOCCTL) | PADEN_SET); - write32(bar + UOCCAP, read32(bar + UOCCAP) | APU_SET); - } - } - - /* Disable virtual PCI UDC and OTG headers */ - dev = dev_find_device(PCI_VENDOR_ID_AMD, - PCI_DEVICE_ID_AMD_CS5536_UDC, 0); - if (dev) { - pci_write_config32(dev, 0x7C, 0xDEADBEEF); - } - - dev = dev_find_device(PCI_VENDOR_ID_AMD, - PCI_DEVICE_ID_AMD_CS5536_OTG, 0); - if (dev) { - pci_write_config32(dev, 0x7C, 0xDEADBEEF); - } -} - -/**************************************************************************** - * - * ChipsetInit - * - * Called from northbridge init (Pre-VSA). - * - ****************************************************************************/ -void chipsetinit(void) -{ - struct device *dev; - msr_t msr; - u32 msrnum; - struct southbridge_amd_cs5536_config *sb; - struct msrinit *csi; - - dev = dev_find_slot(0, PCI_DEVFN(0xf, 0)); - - if (!dev) { - printk(BIOS_ERR, "CS5536 not found.\n"); - return; - } - - sb = (struct southbridge_amd_cs5536_config *)dev->chip_info; - - if (!sb) { - printk(BIOS_ERR, "CS5536 configuration not found.\n"); - return; - } - - post_code(P80_CHIPSET_INIT); - - /* we hope NEVER to be in coreboot when S3 resumes - if (! IsS3Resume()) */ - { - struct acpiinit *aci = acpi_init_table; - for (; aci->ioreg; aci++) { - outl(aci->regdata, aci->ioreg); - inl(aci->ioreg); - } - - pmChipsetInit(); - } - - /* set hd IRQ */ - outl(GPIOL_2_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE); - outl(GPIOL_2_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT); - - /* Allow IO read and writes during a ATA DMA operation. */ - /* This could be done in the HD ROM but do it here for easier debugging. */ - msrnum = ATA_SB_GLD_MSR_ERR; - msr = rdmsr(msrnum); - msr.lo &= ~0x100; - wrmsr(msrnum, msr); - - /* Enable Post Primary IDE. */ - msrnum = GLPCI_SB_CTRL; - msr = rdmsr(msrnum); - msr.lo |= GLPCI_CRTL_PPIDE_SET; - wrmsr(msrnum, msr); - - csi = SB_MASTER_CONF_TABLE; - for (; csi->msrnum; csi++) { - msr.lo = csi->msr.lo; - msr.hi = csi->msr.hi; - wrmsr(csi->msrnum, msr); // MSR - see table above - } - - /* Flash BAR size Setup */ - printk(BIOS_INFO, "%sDoing ChipsetFlashSetup()\n", - sb->enable_ide_nand_flash == 1 ? "" : "Not "); - if (sb->enable_ide_nand_flash == 1) - ChipsetFlashSetup(); - - /* */ - /* Set up Hardware Clock Gating */ - /* */ - { - csi = CS5536_CLOCK_GATING_TABLE; - for (; csi->msrnum; csi++) { - msr.lo = csi->msr.lo; - msr.hi = csi->msr.hi; - wrmsr(csi->msrnum, msr); // MSR - see table above - } - } -} - -static void southbridge_init(struct device *dev) -{ - struct southbridge_amd_cs5536_config *sb = - (struct southbridge_amd_cs5536_config *)dev->chip_info; - int i; - /* - * struct device *gpiodev; - * unsigned short gpiobase = MDD_GPIO; - */ - - printk(BIOS_INFO, "cs5536: %s\n", __func__); - - if (!sb) { - printk(BIOS_ERR, "CS5536 configuration not found.\n"); - return; - } - - setup_i8259(); - lpc_init(sb); - uarts_init(sb); - - if (sb->enable_gpio_int_route) { - vrWrite((VRC_MISCELLANEOUS << 8) + PCI_INT_AB, - (sb->enable_gpio_int_route & 0xFFFF)); - vrWrite((VRC_MISCELLANEOUS << 8) + PCI_INT_CD, - (sb->enable_gpio_int_route >> 16)); - } - - printk(BIOS_DEBUG, "cs5536: %s: enable_ide_nand_flash is %d\n", __func__, - sb->enable_ide_nand_flash); - if (sb->enable_ide_nand_flash == 1) { - enable_ide_nand_flash_header(); - } - - enable_USB_port4(sb); - - /* disable unwanted virtual PCI devices */ - for (i = 0; (i < MAX_UNWANTED_VPCI) && (0 != sb->unwanted_vpci[i]); i++) { - printk(BIOS_DEBUG, "Disabling VPCI device: 0x%08X\n", - sb->unwanted_vpci[i]); - outl(sb->unwanted_vpci[i] + 0x7C, 0xCF8); - outl(0xDEADBEEF, 0xCFC); - } -} - -static void cs5536_read_resources(struct device *dev) -{ - struct resource *res; - - pci_dev_read_resources(dev); - - res = new_resource(dev, 1); - res->base = 0x0UL; - res->size = 0x1000UL; - res->limit = 0xffffUL; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, 3); /* IOAPIC */ - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -} - -static void southbridge_enable(struct device *dev) -{ - printk(BIOS_DEBUG, "cs5536: %s: dev is %p\n", __func__, dev); - -} - -static int lsmbus_read_byte(struct device *dev, u8 address) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x10); - - return do_smbus_read_byte(res->base, device, address); -} - -static struct smbus_bus_operations lops_smbus_bus = { - .read_byte = lsmbus_read_byte, -}; - -static void scan_lpc_smbus(struct device *dev) -{ - /* FIXME. Do we have mixed LPC/SMBus device node here. */ - scan_smbus(dev); -} - -static struct device_operations southbridge_ops = { - .read_resources = cs5536_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = southbridge_init, - .scan_bus = scan_lpc_smbus, - .ops_smbus_bus = &lops_smbus_bus, -}; - -static const struct pci_driver cs5536_pci_driver __pci_driver = { - .ops = &southbridge_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_CS5536_ISA -}; - -struct chip_operations southbridge_amd_cs5536_ops = { - CHIP_NAME("AMD Geode CS5536 Southbridge") - /* This is only called when this device is listed in the - * static device tree. - */ - .enable_dev = southbridge_enable, -}; diff --git a/src/southbridge/amd/cs5536/cs5536.h b/src/southbridge/amd/cs5536/cs5536.h deleted file mode 100644 index 06c504a1aa..0000000000 --- a/src/southbridge/amd/cs5536/cs5536.h +++ /dev/null @@ -1,454 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _CS5536_H -#define _CS5536_H - -#define Cx5536_ID ( 0x208F1022) - -/* SouthBridge Equates */ -#define CS5536_GLINK_PORT_NUM 0x02 /* port of the SouthBridge */ -#define NB_PCI ((2 << 29) + (4 << 26)) /* NB GLPCI is in the same location on all Geodes. */ -#define MSR_SB ((CS5536_GLINK_PORT_NUM << 23) + NB_PCI) /* address to the SouthBridge */ -#define SB_SHIFT 20 /* 29 -> 26 -> 23 -> 20...... When making a SB address uses this shift. */ - -#define CS5536_DEV_NUM 0x0F /* default PCI device number for CS5536 */ -#define SMBUS_IO_BASE 0x6000 -#define GPIO_IO_BASE 0x6100 -#define MFGPT_IO_BASE 0x6200 -#define ACPI_IO_BASE 0x9C00 -#define PMS_IO_BASE 0x9D00 - -#define CS5535_IDSEL 0x02000000 /* IDSEL = AD25, device #15 */ -#define CHIPSET_DEV_NUM 15 -#define IDSEL_BASE 11 /* bit 11 = device 1 */ - -/* Cs5536 as follows. */ -/* SB_GLIU */ -/* port0 - GLIU */ -/* port1 - GLPCI */ -/* port2 - USB Controller #2 */ -/* port3 - ATA-5 Controller */ -/* port4 - MDD */ -/* port5 - AC97 */ -/* port6 - USB Controller #1 */ -/* port7 - GLCP */ - -#define MSR_SB_GLIU ((9 << 14) + MSR_SB) /* 51024xxx or 510*xxxx - fake out just like GL0 on CPU. */ -#define MSR_SB_GLPCI (MSR_SB) /* 5100xxxx - don't go to the GLIU */ -#define MSR_SB_USB2 ((2 << SB_SHIFT) + MSR_SB) /* 5120xxxx */ -#define MSR_SB_ATA ((3 << SB_SHIFT) + MSR_SB) /* 5130xxxx */ -#define MSR_SB_MDD ((4 << SB_SHIFT) + MSR_SB) /* 5140xxxx, a.k.a. DIVIL = Diverse Integrated Logic device */ -#define MSR_SB_AC97 ((5 << SB_SHIFT) + MSR_SB) /* 5150xxxx */ -#define MSR_SB_USB1 ((6 << SB_SHIFT) + MSR_SB) /* 5160xxxx */ -#define MSR_SB_GLCP ((7 << SB_SHIFT) + MSR_SB) /* 5170xxxx */ - -/* GLIU */ -#define GLIU_SB_GLD_MSR_CAP (MSR_SB_GLIU + 0x00) -#define GLIU_SB_GLD_MSR_CONF (MSR_SB_GLIU + 0x01) -#define GLIU_SB_GLD_MSR_PM (MSR_SB_GLIU + 0x04) - -/* USB1 */ -#define USB1_SB_GLD_MSR_CAP (MSR_SB_USB1 + 0x00) -#define USB1_SB_GLD_MSR_CONF (MSR_SB_USB1 + 0x01) -#define USB1_SB_GLD_MSR_PM (MSR_SB_USB1 + 0x04) - -/* USB2 */ -#define USB2_SB_GLD_MSR_CAP (MSR_SB_USB2 + 0x00) -#define USB2_SB_GLD_MSR_CONF (MSR_SB_USB2 + 0x01) -#define USB2_UPPER_SSDEN_SET (1 << 3 ) /* Bit 35 */ -#define USB2_SB_GLD_MSR_PM (MSR_SB_USB2 + 0x04) -#define USB2_SB_GLD_MSR_DIAG (MSR_SB_USB2 + 0x05) -#define USB2_SB_GLD_MSR_OHCI_BASE (MSR_SB_USB2 + 0x08) -#define USB2_SB_GLD_MSR_EHCI_BASE (MSR_SB_USB2 + 0x09) -#define USB2_SB_GLD_MSR_DEVCTL_BASE (MSR_SB_USB2 + 0x0A) -#define USB2_SB_GLD_MSR_UOC_BASE (MSR_SB_USB2 + 0x0B) /* Option controller base */ - -/* ATA */ -#define ATA_SB_GLD_MSR_CAP (MSR_SB_ATA + 0x00) -#define ATA_SB_GLD_MSR_CONF (MSR_SB_ATA + 0x01) -#define ATA_SB_GLD_MSR_ERR (MSR_SB_ATA + 0x03) -#define ATA_SB_GLD_MSR_PM (MSR_SB_ATA + 0x04) -#define ATA_SB_IDE_CFG (MSR_SB_ATA + 0x10) - -/* AC97 */ -#define AC97_SB_GLD_MSR_CAP (MSR_SB_AC97 + 0x00) -#define AC97_SB_GLD_MSR_CONF (MSR_SB_AC97 + 0x01) -#define AC97_SB_GLD_MSR_PM (MSR_SB_AC97 + 0x04) - -/* GLPCI */ -#define GLPCI_SB_GLD_MSR_CAP (MSR_SB_GLPCI + 0x00) -#define GLPCI_SB_GLD_MSR_CONF (MSR_SB_GLPCI + 0x01) -#define GLPCI_SB_GLD_MSR_PM (MSR_SB_GLPCI + 0x04) -#define GLPCI_SB_CTRL (MSR_SB_GLPCI + 0x10) -#define GLPCI_CRTL_PPIDE_SET (1 << 17) - -/* GLCP */ -#define GLCP_SB_GLD_MSR_CAP (MSR_SB_GLCP + 0x00) -#define GLCP_SB_GLD_MSR_CONF (MSR_SB_GLCP + 0x01) -#define GLCP_SB_GLD_MSR_PM (MSR_SB_GLCP + 0x04) -#define GLCP_SB_CLKOFF (MSR_SB_GLCP + 0x10) - -/* MDD */ -#define MDD_SB_GLD_MSR_CAP (MSR_SB_MDD + 0x00) -#define MDD_SB_GLD_MSR_CONF (MSR_SB_MDD + 0x01) -#define MDD_SB_GLD_MSR_PM (MSR_SB_MDD + 0x04) -#define LBAR_EN (0x01) -#define IO_MASK (0x1f) -#define MEM_MASK (0x0FFFFF) -#define MDD_LBAR_IRQ (MSR_SB_MDD + 0x08) -#define MDD_LBAR_KEL1 (MSR_SB_MDD + 0x09) -#define MDD_LBAR_KEL2 (MSR_SB_MDD + 0x0A) -#define MDD_LBAR_SMB (MSR_SB_MDD + 0x0B) -#define MDD_LBAR_GPIO (MSR_SB_MDD + 0x0C) -#define MDD_LBAR_MFGPT (MSR_SB_MDD + 0x0D) -#define MDD_LBAR_ACPI (MSR_SB_MDD + 0x0E) -#define MDD_LBAR_PMS (MSR_SB_MDD + 0x0F) - -#define MDD_LBAR_FLSH0 (MSR_SB_MDD + 0x10) -#define MDD_LBAR_FLSH1 (MSR_SB_MDD + 0x11) -#define MDD_LBAR_FLSH2 (MSR_SB_MDD + 0x12) -#define MDD_LBAR_FLSH3 (MSR_SB_MDD + 0x13) -#define MDD_LEG_IO (MSR_SB_MDD + 0x14) -#define MDD_PIN_OPT (MSR_SB_MDD + 0x15) -#define MDD_SOFT_IRQ (MSR_SB_MDD + 0x16) -#define MDD_SOFT_RESET (MSR_SB_MDD + 0x17) -#define MDD_NORF_CNTRL (MSR_SB_MDD + 0x18) -#define MDD_NORF_T01 (MSR_SB_MDD + 0x19) -#define MDD_NORF_T23 (MSR_SB_MDD + 0x1A) -#define MDD_NANDF_DATA (MSR_SB_MDD + 0x1B) -#define MDD_NADF_CNTL (MSR_SB_MDD + 0x1C) -#define MDD_AC_DMA (MSR_SB_MDD + 0x1E) -#define MDD_KEL_CNTRL (MSR_SB_MDD + 0x1F) - -#define MDD_IRQM_YLOW (MSR_SB_MDD + 0x20) -#define MDD_IRQM_YHIGH (MSR_SB_MDD + 0x21) -#define MDD_IRQM_ZLOW (MSR_SB_MDD + 0x22) -#define MDD_IRQM_ZHIGH (MSR_SB_MDD + 0x23) -#define MDD_IRQM_PRIM (MSR_SB_MDD + 0x24) -#define MDD_IRQM_LPC (MSR_SB_MDD + 0x25) -#define MDD_IRQM_LXIRR (MSR_SB_MDD + 0x26) -#define MDD_IRQM_HXIRR (MSR_SB_MDD + 0x27) - -#define MDD_MFGPT_IRQ (MSR_SB_MDD + 0x28) -#define MDD_MFGPT_NR (MSR_SB_MDD + 0x29) -#define MDD_MFGPT_RES0 (MSR_SB_MDD + 0x2A) -#define MDD_MFGPT_RES1 (MSR_SB_MDD + 0x2B) - -#define MDD_FLOP_S3F2 (MSR_SB_MDD + 0x30) -#define MDD_FLOP_S3F7 (MSR_SB_MDD + 0x31) -#define MDD_FLOP_S372 (MSR_SB_MDD + 0x32) -#define MDD_FLOP_S377 (MSR_SB_MDD + 0x33) - -#define MDD_PIC_S (MSR_SB_MDD + 0x34) -#define MDD_PIT_S (MSR_SB_MDD + 0x36) -#define MDD_PIT_CNTRL (MSR_SB_MDD + 0x37) - -#define MDD_UART1_MOD (MSR_SB_MDD + 0x38) -#define MDD_UART1_DON (MSR_SB_MDD + 0x39) -#define MDD_UART1_CONF (MSR_SB_MDD + 0x3A) -#define MDD_UART2_MOD (MSR_SB_MDD + 0x3C) -#define MDD_UART2_DON (MSR_SB_MDD + 0x3D) -#define MDD_UART2_CONF (MSR_SB_MDD + 0x3E) - -#define MDD_DMA_MAP (MSR_SB_MDD + 0x40) -#define MDD_DMA_SHAD1 (MSR_SB_MDD + 0x41) -#define MDD_DMA_SHAD2 (MSR_SB_MDD + 0x42) -#define MDD_DMA_SHAD3 (MSR_SB_MDD + 0x43) -#define MDD_DMA_SHAD4 (MSR_SB_MDD + 0x44) -#define MDD_DMA_SHAD5 (MSR_SB_MDD + 0x45) -#define MDD_DMA_SHAD6 (MSR_SB_MDD + 0x46) -#define MDD_DMA_SHAD7 (MSR_SB_MDD + 0x47) -#define MDD_DMA_SHAD8 (MSR_SB_MDD + 0x48) -#define MDD_DMA_SHAD9 (MSR_SB_MDD + 0x49) - -#define MDD_LPC_EADDR (MSR_SB_MDD + 0x4C) -#define MDD_LPC_ESTAT (MSR_SB_MDD + 0x4D) -#define MDD_LPC_SIRQ (MSR_SB_MDD + 0x4E) -#define MDD_LPC_RES (MSR_SB_MDD + 0x4F) - -#define MDD_PML_TMR (MSR_SB_MDD + 0x50) -#define MDD_RTC_RAM_LO_CK (MSR_SB_MDD + 0x54) -#define MDD_RTC_DOMA_IND (MSR_SB_MDD + 0x55) -#define MDD_RTC_MONA_IND (MSR_SB_MDD + 0x56) -#define MDD_RTC_CENTURY_OFFSET (MSR_SB_MDD + 0x57) - -/* LBUS Device Equates - */ - -/* SMBus */ -#define SMB_SDA 0x00 -#define SMB_STS 0x01 -#define SMB_STS_SLVSTP (0x01 << 7) -#define SMB_STS_SDAST (0x01 << 6) -#define SMB_STS_BER (0x01 << 5) -#define SMB_STS_NEGACK (0x01 << 4) -#define SMB_STS_STASTR (0x01 << 3) -#define SMB_STS_NMATCH (0x01 << 2) -#define SMB_STS_MASTER (0x01 << 1) -#define SMB_STS_XMIT (0x01 << 0) - -#define SMB_CTRL_STS 0x02 -#define SMB_CSTS_TGSCL (0x01 << 5) -#define SMB_CSTS_TSDA (0x01 << 4) -#define SMB_CSTS_GCMTCH (0x01 << 3) -#define SMB_CSTS_MATCH (0x01 << 2) -#define SMB_CSTS_BB (0x01 << 1) -#define SMB_CSTS_BUSY (0x01 << 0) - -#define SMB_CTRL1 0x03 -#define SMB_CTRL1_STASTRE (0x01 << 7) -#define SMB_CTRL1_NMINTE (0x01 << 6) -#define SMB_CTRL1_GCMEN (0x01 << 5) -#define SMB_CTRL1_ACK (0x01 << 4) -#define SMB_CTRL1_RSVD (0x01 << 3) -#define SMB_CTRL1_INTEN (0x01 << 2) -#define SMB_CTRL1_STOP (0x01 << 1) -#define SMB_CTRL1_START (0x01 << 0) - -#define SMB_ADD 0x04 -#define SMB_ADD_SAEN (0x01 << 7) - -#define SMB_CTRL2 0x05 -#define SMB_CTRL2_ENABLE (0x01 << 0) - -#define SMB_CTRL3 0x06 - -/* GPIO */ -#define GPIOL_0_SET (1 << 0) -#define GPIOL_1_SET (1 << 1) -#define GPIOL_2_SET (1 << 2) -#define GPIOL_3_SET (1 << 3) -#define GPIOL_4_SET (1 << 4) -#define GPIOL_5_SET (1 << 5) -#define GPIOL_6_SET (1 << 6) -#define GPIOL_7_SET (1 << 7) -#define GPIOL_8_SET (1 << 8) -#define GPIOL_9_SET (1 << 9) -#define GPIOL_10_SET (1 << 10) -#define GPIOL_11_SET (1 << 11) -#define GPIOL_12_SET (1 << 12) -#define GPIOL_13_SET (1 << 13) -#define GPIOL_14_SET (1 << 14) -#define GPIOL_15_SET (1 << 15) - -#define GPIOL_0_CLEAR (1 << 16) -#define GPIOL_1_CLEAR (1 << 17) -#define GPIOL_2_CLEAR (1 << 18) -#define GPIOL_3_CLEAR (1 << 19) -#define GPIOL_4_CLEAR (1 << 20) -#define GPIOL_5_CLEAR (1 << 21) -#define GPIOL_6_CLEAR (1 << 22) -#define GPIOL_7_CLEAR (1 << 23) -#define GPIOL_8_CLEAR (1 << 24) -#define GPIOL_9_CLEAR (1 << 25) -#define GPIOL_10_CLEAR (1 << 26) -#define GPIOL_11_CLEAR (1 << 27) -#define GPIOL_12_CLEAR (1 << 28) -#define GPIOL_13_CLEAR (1 << 29) -#define GPIOL_14_CLEAR (1 << 30) -#define GPIOL_15_CLEAR (1 << 31) - -#define GPIOH_16_SET (1 << 0) -#define GPIOH_17_SET (1 << 1) -#define GPIOH_18_SET (1 << 2) -#define GPIOH_19_SET (1 << 3) -#define GPIOH_20_SET (1 << 4) -#define GPIOH_21_SET (1 << 5) -#define GPIOH_22_SET (1 << 6) -#define GPIOH_23_SET (1 << 7) -#define GPIOH_24_SET (1 << 8) -#define GPIOH_25_SET (1 << 9) -#define GPIOH_26_SET (1 << 10) -#define GPIOH_27_SET (1 << 11) -#define GPIOH_28_SET (1 << 12) -#define GPIOH_29_SET (1 << 13) -#define GPIOH_30_SET (1 << 14) -#define GPIOH_31_SET (1 << 15) - -#define GPIOH_16_CLEAR (1 << 16) -#define GPIOH_17_CLEAR (1 << 17) -#define GPIOH_18_CLEAR (1 << 18) -#define GPIOH_19_CLEAR (1 << 19) -#define GPIOH_20_CLEAR (1 << 20) -#define GPIOH_21_CLEAR (1 << 21) -#define GPIOH_22_CLEAR (1 << 22) -#define GPIOH_23_CLEAR (1 << 23) -#define GPIOH_24_CLEAR (1 << 24) -#define GPIOH_25_CLEAR (1 << 25) -#define GPIOH_26_CLEAR (1 << 26) -#define GPIOH_27_CLEAR (1 << 27) -#define GPIOH_28_CLEAR (1 << 28) -#define GPIOH_29_CLEAR (1 << 29) -#define GPIOH_30_CLEAR (1 << 30) -#define GPIOH_31_CLEAR (1 << 31) - -/* GPIO LOW Bank Bit Registers */ -#define GPIOL_OUTPUT_VALUE (0x00) -#define GPIOL_OUTPUT_ENABLE (0x04) -#define GPIOL_OUT_OPENDRAIN (0x08) -#define GPIOL_OUTPUT_INVERT_ENABLE (0x0C) -#define GPIOL_OUT_AUX1_SELECT (0x10) -#define GPIOL_OUT_AUX2_SELECT (0x14) -#define GPIOL_PULLUP_ENABLE (0x18) -#define GPIOL_PULLDOWN_ENABLE (0x1C) -#define GPIOL_INPUT_ENABLE (0x20) -#define GPIOL_INPUT_INVERT_ENABLE (0x24) -#define GPIOL_IN_FILTER_ENABLE (0x28) -#define GPIOL_IN_EVENTCOUNT_ENABLE (0x2C) -#define GPIOL_READ_BACK (0x30) -#define GPIOL_IN_AUX1_SELECT (0x34) -#define GPIOL_EVENTS_ENABLE (0x38) -#define GPIOL_LOCK_ENABLE (0x3C) -#define GPIOL_IN_POSEDGE_ENABLE (0x40) -#define GPIOL_IN_NEGEDGE_ENABLE (0x44) -#define GPIOL_IN_POSEDGE_STATUS (0x48) -#define GPIOL_IN_NEGEDGE_STATUS (0x4C) - -/* GPIO High Bank Bit Registers */ -#define GPIOH_OUTPUT_VALUE (0x80) -#define GPIOH_OUTPUT_ENABLE (0x84) -#define GPIOH_OUT_OPENDRAIN (0x88) -#define GPIOH_OUTPUT_INVERT_ENABLE (0x8C) -#define GPIOH_OUT_AUX1_SELECT (0x90) -#define GPIOH_OUT_AUX2_SELECT (0x94) -#define GPIOH_PULLUP_ENABLE (0x98) -#define GPIOH_PULLDOWN_ENABLE (0x9C) -#define GPIOH_INPUT_ENABLE (0xA0) -#define GPIOH_INPUT_INVERT_ENABLE (0xA4) -#define GPIOH_IN_FILTER_ENABLE (0xA8) -#define GPIOH_IN_EVENTCOUNT_ENABLE (0xAC) -#define GPIOH_READ_BACK (0xB0) -#define GPIOH_IN_AUX1_SELECT (0xB4) -#define GPIOH_EVENTS_ENABLE (0xB8) -#define GPIOH_LOCK_ENABLE (0xBC) -#define GPIOH_IN_POSEDGE_ENABLE (0xC0) -#define GPIOH_IN_NEGEDGE_ENABLE (0xC4) -#define GPIOH_IN_POSEDGE_STATUS (0xC8) -#define GPIOH_IN_NEGEDGE_STATUS (0xCC) - -/* Input Conditioning Function Registers */ -#define GPIO_00_FILTER_AMOUNT (0x50) -#define GPIO_00_FILTER_COUNT (0x52) -#define GPIO_00_EVENT_COUNT (0x54) -#define GPIO_00_EVENTCOMPARE_VALUE (0x56) -#define GPIO_01_FILTER_AMOUNT (0x58) -#define GPIO_01_FILTER_COUNT (0x5A) -#define GPIO_01_EVENT_COUNT (0x5C) -#define GPIO_01_EVENTCOMPARE_VALUE (0x5E) -#define GPIO_02_FILTER_AMOUNT (0x60) -#define GPIO_02_FILTER_COUNT (0x62) -#define GPIO_02_EVENT_COUNT (0x64) -#define GPIO_02_EVENTCOMPARE_VALUE (0x66) -#define GPIO_03_FILTER_AMOUNT (0x68) -#define GPIO_03_FILTER_COUNT (0x6A) -#define GPIO_03_EVENT_COUNT (0x6C) -#define GPIO_03_EVENTCOMPARE_VALUE (0x6E) -#define GPIO_04_FILTER_AMOUNT (0x70) -#define GPIO_04_FILTER_COUNT (0x72) -#define GPIO_04_EVENT_COUNT (0x74) -#define GPIO_04_EVENTCOMPARE_VALUE (0x76) -#define GPIO_05_FILTER_AMOUNT (0x78) -#define GPIO_05_FILTER_COUNT (0x7A) -#define GPIO_05_EVENT_COUNT (0x7C) -#define GPIO_05_EVENTCOMPARE_VALUE (0x7E) -#define GPIO_06_FILTER_AMOUNT (0xD0) -#define GPIO_06_FILTER_COUNT (0xD2) -#define GPIO_06_EVENT_COUNT (0xD4) -#define GPIO_06_EVENTCOMPARE_VALUE (0xD6) -#define GPIO_07_FILTER_AMOUNT (0xD8) -#define GPIO_07_FILTER_COUNT (0xDA) -#define GPIO_07_EVENT_COUNT (0xDC) -#define GPIO_07_EVENTCOMPARE_VALUE (0xDE) - -/* R/W GPIO Interrupt &PME Mapper Registers */ -#define GPIO_MAPPER_X (0xE0) -#define GPIO_MAPPER_Y (0xE4) -#define GPIO_MAPPER_Z (0xE8) -#define GPIO_MAPPER_W (0xEC) -#define GPIO_FE_SELECT_0 (0xF0) -#define GPIO_FE_SELECT_1 (0xF1) -#define GPIO_FE_SELECT_2 (0xF2) -#define GPIO_FE_SELECT_3 (0xF3) -#define GPIO_FE_SELECT_4 (0xF4) -#define GPIO_FE_SELECT_5 (0xF5) -#define GPIO_FE_SELECT_6 (0xF6) -#define GPIO_FE_SELECT_7 (0xF7) - -/* Event Counter Decrement Registers */ -#define GPIOL_IN_EVENT_DECREMENT (0xF8) -#define GPIOH_IN_EVENT_DECREMENT (0xFC) - -/* PMC register */ -#define PM_SSD (0x00) -#define PM_SCXA (0x04) -#define PM_SCYA (0x08) -#define PM_SODA (0x0C) -#define PM_SCLK (0x10) -#define PM_SED (0x14) -#define PM_SCXD (0x18) -#define PM_SCYD (0x1C) -#define PM_SIDD (0x20) -#define PM_WKD (0x30) -#define PM_WKXD (0x34) -#define PM_RD (0x38) -#define PM_WKXA (0x3C) -#define PM_FSD (0x40) -#define PM_TSD (0x44) -#define PM_PSD (0x48) -#define PM_NWKD (0x4C) -#define PM_AWKD (0x50) -#define PM_SSC (0x54) - -/* FLASH device macros */ -#define FLASH_TYPE_NONE 0 /* No flash device installed */ -#define FLASH_TYPE_NAND 1 /* NAND device */ -#define FLASH_TYPE_NOR 2 /* NOR device */ - -#define FLASH_IF_MEM 1 /* Memory or memory-mapped I/O interface for Flash device */ -#define FLASH_IF_IO 2 /* I/O interface for Flash device */ - -/* Flash Memory Mask values */ -#define FLASH_MEM_DEFAULT 0x00000000 -#define FLASH_MEM_4K 0xFFFFF000 -#define FLASH_MEM_8K 0xFFFFE000 -#define FLASH_MEM_16K 0xFFFFC000 -#define FLASH_MEM_128K 0xFFFE0000 -#define FLASH_MEM_512K 0xFFFC0000 -#define FLASH_MEM_4M 0xFFC00000 -#define FLASH_MEM_8M 0xFF800000 -#define FLASH_MEM_16M 0xFF000000 - -/* Flash IO Mask values */ -#define FLASH_IO_DEFAULT 0x00000000 -#define FLASH_IO_16B 0x0000FFF0 -#define FLASH_IO_32B 0x0000FFE0 -#define FLASH_IO_64B 0x0000FFC0 -#define FLASH_IO_128B 0x0000FF80 -#define FLASH_IO_256B 0x0000FF00 - -#if !defined(__ASSEMBLER__) -#if defined(__PRE_RAM__) -void cs5536_setup_onchipuart(int uart); -void cs5536_disable_internal_uart(void); -void cs5536_early_setup(void); - -void cs5536_enable_smbus(void); -int smbus_read_byte(unsigned int device, unsigned int address); -#else -void chipsetinit(void); -#endif -#endif - -#endif /* _CS5536_H */ diff --git a/src/southbridge/amd/cs5536/early_setup.c b/src/southbridge/amd/cs5536/early_setup.c deleted file mode 100644 index a95a0b4521..0000000000 --- a/src/southbridge/amd/cs5536/early_setup.c +++ /dev/null @@ -1,276 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * cs5536_early_setup.c: Early chipset initialization for CS5536 companion device - * This file implements the initialization sequence documented in section 4.2 of - * AMD Geode GX Processor CS5536 Companion Device GeodeROM Porting Guide. - */ - -#include <arch/io.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/lxdef.h> -#include "cs5536.h" - -/** - * @brief Setup PCI IDSEL for CS5536 - */ -static void cs5536_setup_extmsr(void) -{ - msr_t msr; - - /* forward MSR access to CS5536_GLINK_PORT_NUM to CS5536_DEV_NUM */ - msr.hi = msr.lo = 0x00000000; -#if CS5536_GLINK_PORT_NUM <= 4 - msr.lo = CS5536_DEV_NUM << (unsigned char)((CS5536_GLINK_PORT_NUM - 1) * 8); -#else - msr.hi = CS5536_DEV_NUM << (unsigned char)((CS5536_GLINK_PORT_NUM - 5) * 8); -#endif - wrmsr(GLPCI_ExtMSR, msr); -} - -static void cs5536_setup_idsel(void) -{ - /* write IDSEL to the write once register at address 0x0000 */ - outl(0x1 << (CS5536_DEV_NUM + 10), 0); -} - -static void cs5536_usb_swapsif(void) -{ - msr_t msr; - - msr = rdmsr(USB1_SB_GLD_MSR_CAP + 0x5); - //USB Serial short detect bit. - if (msr.hi & 0x10) { - /* We need to preserve bits 32,33,35 and not clear any BIST - * error, but clear the SERSHRT error bit */ - - msr.hi &= 0xFFFFFFFB; - wrmsr(USB1_SB_GLD_MSR_CAP + 0x5, msr); - } -} - -static void cs5536_setup_iobase(void) -{ - msr_t msr; - /* setup LBAR for SMBus controller */ - msr.hi = 0x0000f001; - msr.lo = SMBUS_IO_BASE; - wrmsr(MDD_LBAR_SMB, msr); - - /* setup LBAR for GPIO */ - msr.hi = 0x0000f001; - msr.lo = GPIO_IO_BASE; - wrmsr(MDD_LBAR_GPIO, msr); - - /* setup LBAR for MFGPT */ - msr.hi = 0x0000f001; - msr.lo = MFGPT_IO_BASE; - wrmsr(MDD_LBAR_MFGPT, msr); - - /* setup LBAR for ACPI */ - msr.hi = 0x0000f001; - msr.lo = ACPI_IO_BASE; - wrmsr(MDD_LBAR_ACPI, msr); - - /* setup LBAR for PM Support */ - msr.hi = 0x0000f001; - msr.lo = PMS_IO_BASE; - wrmsr(MDD_LBAR_PMS, msr); -} - -static void cs5536_setup_power_button(void) -{ -#if IS_ENABLED(CONFIG_ENABLE_POWER_BUTTON) - outl(0x40020000, PMS_IO_BASE + 0x40); -#endif - - /* setup WORK_AUX/GPIO24, it is the external signal for 5536 - * vsb_work_aux controls all voltage rails except Vstandby & Vmem. - * We need to enable, OUT_AUX1 and OUTPUT_ENABLE in this order. - * If WORK_AUX/GPIO24 is not enabled then soft-off will not work. - */ - outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUT_AUX1_SELECT); - outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE); - -} - -static void cs5536_setup_gpio(void) -{ - uint32_t val; - - /* setup GPIO pins 14/15 for SDA/SCL */ - val = GPIOL_15_SET | GPIOL_14_SET; - /* Output Enable */ - outl(val, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT); - /* Output AUX1 */ - outl(val, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE); - /* Input Enable */ - outl(val, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT); - /* Input AUX1 */ - outl(val, GPIO_IO_BASE + GPIOL_INPUT_ENABLE); -} - -void cs5536_disable_internal_uart(void) -{ - msr_t msr; - /* The UARTs default to enabled. - * Disable and reset them and configure them later. (SIO init) - */ - msr = rdmsr(MDD_UART1_CONF); - msr.lo = 1; // reset - wrmsr(MDD_UART1_CONF, msr); - msr.lo = 0; // disabled - wrmsr(MDD_UART1_CONF, msr); - - msr = rdmsr(MDD_UART2_CONF); - msr.lo = 1; // reset - wrmsr(MDD_UART2_CONF, msr); - msr.lo = 0; // disabled - wrmsr(MDD_UART2_CONF, msr); -} - -static void cs5536_setup_cis_mode(void) -{ - msr_t msr; - - /* Setup CPU serial SouthBridge interface to mode C. */ - msr = rdmsr(GLPCI_SB_CTRL); - msr.lo &= ~0x18; - msr.lo |= 0x10; - wrmsr(GLPCI_SB_CTRL, msr); -} - -/** - * Enable the on-chip UART. - * - * See page 412 of the AMD Geode CS5536 Companion Device data book. - */ -static void cs5536_setup_onchipuart1(void) -{ - msr_t msr; - - /* Setup early for polling only mode. - * 1. Enable GPIO 8 to OUT_AUX1, 9 to IN_AUX1. - * GPIO LBAR + 0x04, LBAR + 0x10, LBAR + 0x20, LBAR + 34 - * 2. Enable UART I/O space in MDD. - * MSR 0x51400014 bit 18:16 - * 3. Enable UART controller. - * MSR 0x5140003A bit 0, 1 - */ - - /* GPIO8 - UART1_TX */ - /* Set: Output Enable (0x4) */ - outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE); - /* Set: OUTAUX1 Select (0x10) */ - outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT); - - /* GPIO9 - UART1_RX */ - /* Set: Input Enable (0x20) */ - outl(GPIOL_9_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE); - /* Set: INAUX1 Select (0x34) */ - outl(GPIOL_9_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT); - - /* Set address to 0x3F8. */ - msr = rdmsr(MDD_LEG_IO); - msr.lo |= 0x7 << 16; - wrmsr(MDD_LEG_IO, msr); - - /* Bit 1 = DEVEN (device enable) - * Bit 4 = EN_BANKS (allow access to the upper banks) - */ - msr.lo = (1 << 4) | (1 << 1); - msr.hi = 0; - - /* Enable COM1. */ - wrmsr(MDD_UART1_CONF, msr); -} - -static void cs5536_setup_onchipuart2(void) -{ - msr_t msr; - - /* GPIO4 - UART2_TX */ - /* Set: Output Enable (0x4) */ - outl(GPIOL_4_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE); - /* Set: OUTAUX1 Select (0x10) */ - outl(GPIOL_4_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT); - /* GPIO4 - UART2_RX */ - /* Set: Input Enable (0x20) */ - outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE); - /* Set: INAUX1 Select (0x34) */ - outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT); - - /* Set: GPIO 3 + 3 Pull Up (0x18) */ - outl(GPIOL_3_SET | GPIOL_4_SET, - GPIO_IO_BASE + GPIOL_PULLUP_ENABLE); - - /* set address to 2F8 */ - msr = rdmsr(MDD_LEG_IO); - msr.lo |= 0x5 << 20; - wrmsr(MDD_LEG_IO, msr); - - /* Bit 1 = DEVEN (device enable) - * Bit 4 = EN_BANKS (allow access to the upper banks - */ - msr.lo = (1 << 4) | (1 << 1); - msr.hi = 0; - - /* enable COM2 */ - wrmsr(MDD_UART2_CONF, msr); -} - -void cs5536_setup_onchipuart(int uart) -{ - switch (uart) { - case 1: - cs5536_setup_onchipuart1(); - break; - case 2: - cs5536_setup_onchipuart2(); - break; - } -} - - -/* note: you can't do prints in here in most cases, - * and we don't want to hang on serial, so they are - * commented out - */ -void cs5536_early_setup(void) -{ - msr_t msr; - - cs5536_setup_extmsr(); - cs5536_setup_cis_mode(); - - msr = rdmsr(GLCP_SYS_RSTPLL); - if (msr.lo & (0x3f << 26)) { - /* PLL is already set and we are reboot from PLL reset */ - //printk(BIOS_DEBUG, "reboot from BIOS reset\n"); - return; - } - //printk(BIOS_DEBUG, "Setup idsel\n"); - cs5536_setup_idsel(); - //printk(BIOS_DEBUG, "Setup iobase\n"); - cs5536_usb_swapsif(); - cs5536_setup_iobase(); - //printk(BIOS_DEBUG, "Setup gpio\n"); - cs5536_setup_gpio(); - //printk(BIOS_DEBUG, "Setup smbus\n"); - cs5536_enable_smbus(); - //printk(BIOS_DEBUG, "Setup power button\n"); - cs5536_setup_power_button(); -} diff --git a/src/southbridge/amd/cs5536/early_smbus.c b/src/southbridge/amd/cs5536/early_smbus.c deleted file mode 100644 index a1cf50bb15..0000000000 --- a/src/southbridge/amd/cs5536/early_smbus.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include "cs5536.h" -#include "smbus.h" - -/* initialization for SMBus Controller */ -void cs5536_enable_smbus(void) -{ - - if (IS_ENABLED(CONFIG_NO_EARLY_SMBUS)) - return; - - /* Set SCL freq and enable SMB controller */ - /*outb((0x20 << 1) | SMB_CTRL2_ENABLE, smbus_io_base + SMB_CTRL2); */ - outb((0x7F << 1) | SMB_CTRL2_ENABLE, SMBUS_IO_BASE + SMB_CTRL2); - - /* Setup SMBus host controller address to 0xEF */ - outb((0xEF | SMB_ADD_SAEN), SMBUS_IO_BASE + SMB_ADD); - -} - -int smbus_read_byte(unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} diff --git a/src/southbridge/amd/cs5536/ide.c b/src/southbridge/amd/cs5536/ide.c deleted file mode 100644 index 53723e6a5a..0000000000 --- a/src/southbridge/amd/cs5536/ide.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "cs5536.h" - -#define IDE_CFG 0x40 - #define CHANEN (1L << 1) - #define PWB (1L << 14) - #define CABLE (1L << 16) -#define IDE_DTC 0x48 -#define IDE_CAST 0x4C -#define IDE_ETC 0x50 - -static void ide_init(struct device *dev) -{ - uint32_t ide_cfg; - - printk(BIOS_SPEW, "cs5536_ide: %s\n", __func__); - /* GPIO and IRQ setup are handled in the main chipset code. */ - - // Enable the channel and Post Write Buffer - // NOTE: Only 32-bit writes to the data buffer are allowed when PWB is set - ide_cfg = pci_read_config32(dev, IDE_CFG); - ide_cfg |= CHANEN | PWB; - pci_write_config32(dev, IDE_CFG, ide_cfg); -} - -static struct device_operations ide_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .enable = 0, -}; - -static const struct pci_driver ide_driver __pci_driver = { - .ops = &ide_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_CS5536_B0_IDE, -}; diff --git a/src/southbridge/amd/cs5536/pirq.c b/src/southbridge/amd/cs5536/pirq.c deleted file mode 100644 index 75bb16853a..0000000000 --- a/src/southbridge/amd/cs5536/pirq.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/pirq_routing.h> -#include <device/pci.h> -#include <device/pci_ids.h> - -#if IS_ENABLED(CONFIG_PIRQ_ROUTE) && IS_ENABLED(CONFIG_GENERATE_PIRQ_TABLE) -void pirq_assign_irqs(const unsigned char pIntAtoD[4]) -{ - struct device *pdev; - - pdev = dev_find_device(PCI_VENDOR_ID_AMD, - PCI_DEVICE_ID_AMD_CS5536_ISA, 0); - - if (pdev) { - pci_write_config16(pdev, 0x5c, (pIntAtoD[3] << 12 - | pIntAtoD[2] << 8 | pIntAtoD[1] << 4 | pIntAtoD[0])); - } -} -#endif diff --git a/src/southbridge/amd/cs5536/smbus.c b/src/southbridge/amd/cs5536/smbus.c deleted file mode 100644 index ddbcdf2683..0000000000 --- a/src/southbridge/amd/cs5536/smbus.c +++ /dev/null @@ -1,187 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <arch/io.h> -#include "cs5536.h" -#include "smbus.h" - -#define SMBUS_TIMEOUT (1000) - -static void smbus_delay(void) -{ - /* inb(0x80); */ -} - -static int smbus_wait(unsigned smbus_io_base) -{ - unsigned long loops = SMBUS_TIMEOUT; - unsigned char val; - - do { - smbus_delay(); - val = inb(smbus_io_base + SMB_STS); - if ((val & SMB_STS_SDAST) != 0) - break; - if (val & (SMB_STS_BER | SMB_STS_NEGACK)) { - /*printk(BIOS_DEBUG, "SMBUS WAIT ERROR %x\n", val); */ - return SMBUS_ERROR; - } - } while (--loops); - return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT; -} - -/* generate a smbus start condition */ -int smbus_start_condition(unsigned smbus_io_base) -{ - unsigned char val; - - /* issue a START condition */ - val = inb(smbus_io_base + SMB_CTRL1); - outb(val | SMB_CTRL1_START, smbus_io_base + SMB_CTRL1); - - /* check for bus conflict */ - val = inb(smbus_io_base + SMB_STS); - if ((val & SMB_STS_BER) != 0) - return SMBUS_ERROR; - - return smbus_wait(smbus_io_base); -} - -int smbus_check_stop_condition(unsigned smbus_io_base) -{ - unsigned char val; - unsigned long loops; - loops = SMBUS_TIMEOUT; - /* check for SDA status */ - do { - smbus_delay(); - val = inb(smbus_io_base + SMB_CTRL1); - if ((val & SMB_CTRL1_STOP) == 0) { - break; - } - outb((0x7F << 1) | SMB_CTRL2_ENABLE, smbus_io_base + SMB_CTRL2); - } while (--loops); - return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT; -} - -int smbus_stop_condition(unsigned smbus_io_base) -{ - outb(SMB_CTRL1_STOP, smbus_io_base + SMB_CTRL1); - return smbus_wait(smbus_io_base); -} - -static int smbus_ack(unsigned smbus_io_base, int state) -{ - unsigned char val = inb(smbus_io_base + SMB_CTRL1); - -/* if (state) */ - outb(val | SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1); -/* else - outb(val & ~SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1); -*/ - return 0; -} - -int smbus_send_slave_address(unsigned smbus_io_base, - unsigned char device) -{ - unsigned char val; - - /* send the slave address */ - outb(device, smbus_io_base + SMB_SDA); - - /* check for bus conflict and NACK */ - val = inb(smbus_io_base + SMB_STS); - if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0)) { - /* printk(BIOS_DEBUG, "SEND SLAVE ERROR (%x)\n", val); */ - return SMBUS_ERROR; - } - return smbus_wait(smbus_io_base); -} - -int smbus_send_command(unsigned smbus_io_base, unsigned char command) -{ - unsigned char val; - - /* send the command */ - outb(command, smbus_io_base + SMB_SDA); - - /* check for bus conflict and NACK */ - val = inb(smbus_io_base + SMB_STS); - if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0)) - return SMBUS_ERROR; - - return smbus_wait(smbus_io_base); -} - -static unsigned char smbus_get_result(unsigned smbus_io_base) -{ - return inb(smbus_io_base + SMB_SDA); -} - -unsigned char do_smbus_read_byte(unsigned smbus_io_base, - unsigned char device, - unsigned char address) -{ - unsigned char error = 0; - - if ((smbus_check_stop_condition(smbus_io_base))) { - error = 1; - goto err; - } - - if ((smbus_start_condition(smbus_io_base))) { - error = 2; - goto err; - } - - if ((smbus_send_slave_address(smbus_io_base, device << 1))) { - error = 3; - goto err; - } - - smbus_ack(smbus_io_base, 1); - - if ((smbus_send_command(smbus_io_base, address))) { - error = 4; - goto err; - } - - if ((smbus_start_condition(smbus_io_base))) { - error = 5; - goto err; - } - - if ((smbus_send_slave_address(smbus_io_base, (device << 1) | 0x01))) { - error = 6; - goto err; - } - - if ((smbus_stop_condition(smbus_io_base))) { - error = 7; - goto err; - } - - return smbus_get_result(smbus_io_base); - -err: - printk(BIOS_DEBUG, "SMBUS READ ERROR: %02x device: %02x\n", error, device); - /* stop, clean up the error, and leave */ - smbus_stop_condition(smbus_io_base); - outb(inb(smbus_io_base + SMB_STS), smbus_io_base + SMB_STS); - outb(0x0, smbus_io_base + SMB_STS); - return 0xFF; -} diff --git a/src/southbridge/amd/cs5536/smbus.h b/src/southbridge/amd/cs5536/smbus.h deleted file mode 100644 index 3d67acee10..0000000000 --- a/src/southbridge/amd/cs5536/smbus.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _CS5536_SMBUS_H -#define _CS5536_SMBUS_H - -#include <device/smbus_def.h> - -int smbus_start_condition(unsigned smbus_io_base); -int smbus_stop_condition(unsigned smbus_io_base); -int smbus_check_stop_condition(unsigned smbus_io_base); -int smbus_send_slave_address(unsigned smbus_io_base, - unsigned char device); -int smbus_send_command(unsigned smbus_io_base, unsigned char command); - -unsigned char do_smbus_read_byte(unsigned smbus_io_base, - unsigned char device, - unsigned char address); - -#endif /* _CS5536_SMBUS_H */ |