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-rw-r--r--src/southbridge/amd/agesa/hudson/fadt.c16
-rw-r--r--src/southbridge/amd/agesa/hudson/hudson.c33
2 files changed, 33 insertions, 16 deletions
diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c
index fcfbb44580..f86016ab8b 100644
--- a/src/southbridge/amd/agesa/hudson/fadt.c
+++ b/src/southbridge/amd/agesa/hudson/fadt.c
@@ -65,9 +65,6 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->preferred_pm_profile = FADT_PM_PROFILE;
fadt->sci_int = 9; /* HUDSON - IRQ 09 – ACPI SCI */
- /* We write to this port further down; configure it first */
- pm_write16(0x62, ACPI_PM1_CNT_BLK);
-
if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
fadt->smi_cmd = ACPI_SMI_CTL_PORT;
fadt->acpi_enable = ACPI_SMI_CMD_ENABLE;
@@ -75,7 +72,6 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->s4bios_req = 0; /* Not supported */
fadt->pstate_cnt = 0; /* Not supported */
fadt->cst_cnt = 0; /* Not supported */
- hudson_enable_acpi_cmd_smi();
outl(0x0, ACPI_PM1_CNT_BLK); /* clear SCI_EN */
} else {
fadt->smi_cmd = 0; /* disable system management mode */
@@ -87,18 +83,6 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
}
- pm_write16(0x60, ACPI_PM_EVT_BLK);
- pm_write16(0x64, ACPI_PM_TMR_BLK);
- pm_write16(0x68, ACPI_GPE0_BLK);
- /* CpuControl is in \_PR.CPU0, 6 bytes */
- pm_write16(0x66, ACPI_CPU_CONTROL);
- pm_write16(0x6a, fadt->smi_cmd);
-
- pm_write8(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses
- * the contents of the PM registers at
- * index 60-6B to decode ACPI I/O address.
- * AcpiSmiEn & SmiCmdEn*/
-
fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
fadt->pm1b_evt_blk = 0x0000;
fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c
index 39dab23d0d..0edca6eafe 100644
--- a/src/southbridge/amd/agesa/hudson/hudson.c
+++ b/src/southbridge/amd/agesa/hudson/hudson.c
@@ -29,6 +29,7 @@
#include <cbmem.h>
#include "hudson.h"
#include "smbus.h"
+#include "smi.h"
/* Offsets from ACPI_MMIO_BASE
* This is defined by AGESA, but we don't include AGESA headers to avoid
@@ -129,7 +130,39 @@ unsigned long get_top_of_ram(void)
}
#endif
+static void hudson_init_acpi_ports(void)
+{
+ /* We use some of these ports in SMM regardless of whether or not
+ * ACPI tables are generated. Enable these ports indiscriminately.
+ */
+
+ pm_write16(0x60, ACPI_PM_EVT_BLK);
+ pm_write16(0x62, ACPI_PM1_CNT_BLK);
+ pm_write16(0x64, ACPI_PM_TMR_BLK);
+ pm_write16(0x68, ACPI_GPE0_BLK);
+ /* CpuControl is in \_PR.CPU0, 6 bytes */
+ pm_write16(0x66, ACPI_CPU_CONTROL);
+
+ if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
+ pm_write16(0x6a, ACPI_SMI_CTL_PORT);
+ hudson_enable_acpi_cmd_smi();
+ } else {
+ pm_write16(0x6a, 0);
+ }
+
+ /* AcpiDecodeEnable, When set, SB uses the contents of the PM registers
+ * at index 60-6B to decode ACPI I/O address. AcpiSmiEn & SmiCmdEn
+ */
+ pm_write8(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2);
+}
+
+static void hudson_init(void *chip_info)
+{
+ hudson_init_acpi_ports();
+}
+
struct chip_operations southbridge_amd_agesa_hudson_ops = {
CHIP_NAME("ATI HUDSON")
.enable_dev = hudson_enable,
+ .init = hudson_init
};