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-rw-r--r--src/southbridge/intel/common/smi.c26
1 files changed, 26 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c
index af9dd5d87d..40f5412a91 100644
--- a/src/southbridge/intel/common/smi.c
+++ b/src/southbridge/intel/common/smi.c
@@ -154,3 +154,29 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
"d" (APM_CNT)
);
}
+
+void southbridge_smm_clear_state(void)
+{
+ u32 smi_en;
+
+ if (IS_ENABLED(CONFIG_ELOG))
+ /* Log events from chipset before clearing */
+ pch_log_state();
+
+ printk(BIOS_DEBUG, "Initializing Southbridge SMI...\n");
+ printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", get_pmbase());
+
+ smi_en = inl(get_pmbase() + SMI_EN);
+ if (smi_en & APMC_EN) {
+ printk(BIOS_INFO, "SMI# handler already enabled?\n");
+ return;
+ }
+
+ printk(BIOS_DEBUG, "\n");
+
+ /* Dump and clear status registers */
+ reset_smi_status();
+ reset_pm1_status();
+ reset_tco_status();
+ reset_gpe0_status();
+}