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-rw-r--r--src/southbridge/intel/bd82x6x/early_pch.c2
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c3
-rw-r--r--src/southbridge/intel/i82801gx/lpc.c3
-rw-r--r--src/southbridge/intel/ibexpeak/early_pch.c2
-rw-r--r--src/southbridge/intel/ibexpeak/lpc.c3
-rw-r--r--src/southbridge/intel/lynxpoint/early_pch.c2
-rw-r--r--src/southbridge/intel/lynxpoint/lpc.c3
7 files changed, 3 insertions, 15 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c
index 452adb1033..767d3ad936 100644
--- a/src/southbridge/intel/bd82x6x/early_pch.c
+++ b/src/southbridge/intel/bd82x6x/early_pch.c
@@ -222,7 +222,7 @@ static void pch_enable_bars(void)
pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1);
- pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80);
+ pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN);
pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index a498f870a0..8af80654e9 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -44,9 +44,6 @@ static void pch_enable_ioapic(struct device *dev)
pci_write_config16(dev, LPC_IBDF,
PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3);
- /* Enable ACPI I/O range decode */
- pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
-
set_ioapic_id(VIO_APIC_VADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 721735cb15..9ac894254c 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -35,9 +35,6 @@
*/
static void i82801gx_enable_ioapic(struct device *dev)
{
- /* Enable ACPI I/O range decode */
- pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
-
set_ioapic_id(VIO_APIC_VADDR, 0x02);
/*
diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c
index ace09e292f..df380c5bde 100644
--- a/src/southbridge/intel/ibexpeak/early_pch.c
+++ b/src/southbridge/intel/ibexpeak/early_pch.c
@@ -33,7 +33,7 @@ void ibexpeak_setup_bars(void)
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
/* Enable ACPI BAR */
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80);
+ pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN);
printk(BIOS_DEBUG, " done.\n");
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index dddecd79d0..d2a3404880 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -39,9 +39,6 @@ static void pch_enable_ioapic(struct device *dev)
{
u32 reg32;
- /* Enable ACPI I/O range decode */
- pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
-
set_ioapic_id(VIO_APIC_VADDR, 0x01);
/* affirm full set of redirection table entries ("write once") */
reg32 = io_apic_read(VIO_APIC_VADDR, 0x01);
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index 465aa1e710..8cc6a8760c 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -40,7 +40,7 @@ static void pch_enable_bars(void)
pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1);
/* Enable ACPI BAR */
- pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80);
+ pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN);
pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 2872a0b556..2db4b59006 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -41,9 +41,6 @@ static void pch_enable_ioapic(struct device *dev)
pci_write_config16(dev, LPC_IBDF,
PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3);
- /* Enable ACPI I/O range decode */
- pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
-
set_ioapic_id(VIO_APIC_VADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */